Hydrogen anneal for creating an enhanced trench for trench MOSFETS

• US 6,825,087 B1
• Filed: 11/24/1999
• Issued: 11/30/2004
• Est. Priority Date: 11/24/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Sharp, Joelle, Madson, Gordon K.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Vu, David
• Application Number:
  US09/448,884
• Time in Patent Office: 1,833 Days
• Field of Search: 438/243-249, 438/270, 438/296, 438/386-392, 438/424, 438/445, 438/212-213, 438/489
• US Class Current: 438/296
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a trench in a substrate or in an epitaxial layer, previously grown over the semiconductor substrate, wherein an anneal step, using hydrogen gas results in rounded corners without the need for a rounding etch or any other processing steps to round the corners.

Claims

1. A method of forming a trench in a semiconductor substrate, the trench defined by an open end at a major surface of the substrate and a closed end within the body of the substrate, the method comprising the steps of:

(a) forming a trench that extends a predetermined distance into the substrate; and

(b) annealing the trench using hydrogen gas in the absence of oxygen gas to;

(1) round corners at the open and closed ends of the trench, and

(2) reduce oxygen of a native oxide layer on walls of the trench.

2. The method of claim 1 further comprising growing a dielectric layer on the walls of the trench.

3. The method of claim 2 further comprising forming a conductor over the dielectric layer.

4. The method of claim 1, wherein the step of annealing is performed within a temperature range of about 960 to 1160°

C. and within a pressure range of about 40 to 240 Torr.

5. The method of claim 1, wherein the step of forming the trench, is performed using an anisotropic etch.

6. The method of claim 5, wherein following the annealing step, the width of the trench away from the rounded ends, remains substantially the same as the width prior to the annealing step.

7. A method of forming a trench in a semiconductor substrate, the trench defined by an open end at a major surface of the substrate and by a closed end within the body of the substrate, the method comprising the steps of:

(a) providing a substrate;

(b) growing a masking layer on the major surface of the substrate;

(c) selectively etching, through the masking layer to the major surface of the substrate, to define a trench opening access;

(d) anisotropically etching, from the trench opening access and into the body of the substrate to form a trench;

(e) removing the selectively etched masking layer; and

(f) annealing the trench using hydrogen gas in the absence of oxygen gas so that corners at the open and closed ends of the trench become rounded and to reduce oxygen of a native oxide layer on walls of the trench.

8. The method of claim 7, wherein the step of annealing is performed within a temperature range of about 960 to 1160°

C. and within a pressure range of about 40 to 240 Torr.

9. A method of forming a trench in an epitaxial layer of a semiconductor substrate, the trench defined by a closed end at a major surface of the epitaxial layer and a closed end within the body of the epitaxial layer, the method comprising the steps of:

(a) forming a trench that extends a predetermined distance into the epitaxial layer; and

(b) annealing the trench using hydrogen gas in the absence of oxygen gas so that corners at the open and closed ends of the trench become rounded.

10. The method of claim 9, wherein the step of annealing is performed within a temperature range of about 960 to 1160°

C. and within a pressure range of about 40 to 240 Torr.

11. The method of claim 9, wherein the step of annealing also functions to reduce the number of material defects in and/or on the walls of the trench.

12. The method of claim 9, wherein the step of forming the trench is performed using an anisotropic etch.

13. The method of claim 12, wherein, following the annealing step, the width of the trench, away from the rounded ends, remains substantially the same as the width prior to the annealing step.

14. A method of making a trench field effect transistor, comprising:

(a) providing a semiconductor substrate of a first dopant charge type, the substrate embodying the drain of the trench field effect transistor;

(b) growing an epitaxial layer of the same first dopant charge type on the substrate, the epitaxial layer having a different resistivity than the resistivity of the substrate;

(c) forming at least one trench into the epitaxial layer, each trench defined by a first end in a plane defined by a major surface of the substrate and by walls that extend to a second end at a predetermined depth into the epitaxial layer;

(d) annealing the at least one trench using hydrogen gas in the absence of oxygen gas to;

(1) round corners at the first and second ends of the at least one trench, and

(2) reduce oxygen of a native oxide layer on the walls of the at least one trench;

(e) growing a dielectric layer on the walls of the at least one trench;

(f) forming a conductor over the dielectric layer, the conductor embodying the gate of the trench field effect transistor;

(g) patterning the epitaxial layer and implanting a dopant of a second charge type to form wells interposed between adjacent trenches; and

(h) patterning the epitaxial layer and implanting a dopant of the first charge type to form regions that embody the source regions of the field effect transistor.

15. The method of claim 14, further including the step of forming one or more heavy bodies of the second charge type positioned above the wells and between the source regions, each heavy body forming an abrupt junction with its corresponding well.

16. The method of claim 14, wherein the step of annealing is performed within a temperature range of about 960 to 1160°

C. and within a pressure range of about 40 to 240 Torr.

17. The method of claim 14, wherein the step of forming the at least one trench is performed using an anisotropic etch.

18. A method of forming a trench in a semiconductor substrate, the trench defined by an open end at a major surface of the substrate and a closed end within the body of the substrate, the method comprising the steps of:

(a) forming a trench that extends a predetermined distance into the substrate; and

(b) annealing the trench to;

(1) reduce the number of defects in the trench created during the step of forming, and

(2) round corners at the open and closed ends of the trench,

wherein the step of annealing is performed using hydrogen gas within a temperature range of about 960 to 1160°

C. and within a pressure range of about 40 to 240 Torr.