Method of manufacturing a semiconductor device

• US 6,825,492 B2
• Filed: 02/11/2004
• Issued: 11/30/2004
• Est. Priority Date: 04/09/2001
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yonezawa, Masato, Kimura, Hajime, Watanabe, Yasuko, Koyama, Jun, Yamazaki, Yu
• Primary Examiner(s): Pham, Long
• Application Number:
  US10/775,128
• Publication Number:
  US 20040157432A1
• Time in Patent Office: 293 Days
• Field of Search: 257/52, 257/53, 257/57
• US Class Current: 257/53
• CPC Class Codes: G06Q 30/02 Marketing; Price estimation or determination; Fundraising
• CPC Class Codes: G06Q 30/0256 User search
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14678 Contact-type imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays

Abstract

The number of masks is reduced in a method of manufacturing a semiconductor device that has a transistor and a photoelectric conversion element on an insulating surface. In a manufacturing method of the present invention, semiconductor layers functioning as a source region, a drain region, and a channel formation region of a transistor are formed at the same time an n type semiconductor layer and p type semiconductor layer of a photoelectric conversion element are formed. Connection wiring lines to be electrically connected to the n type semiconductor layer and p type semiconductor layer of the photoelectric conversion element are formed at the same time a source wiring line and a drain wiring line of a transistor are formed. In a doping step using an impurity element that gives one conductivity type, a semiconductor layer of an n-channel transistor and the n type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element and a semiconductor layer of a p-channel transistor and the p type semiconductor layer of the photoelectric conversion element are simultaneously doped with the impurity element.

Claims

1. A semiconductor device comprising:

at least one thin film transistor having a first crystalline semiconductor layer formed on an insulating surface, said first crystalline semiconductor layer including a channel formation region therein; and

a photoelectric conversion element electrically connected to said thin film transistor, said photoelectric conversion element comprising;

a second n-type crystalline semiconductor layer formed on said insulating surface;

a third p-type crystalline semiconductor layer formed on said insulating surface; and

an amorphous semiconductor layer formed on and extending between the second n-type crystalline semiconductor layer and the third p-type crystalline semiconductor layer.

2. The semiconductor device according to claim 1 wherein said thin film transistor is selected from the group consisting of an amplifying transistor, a selecting transistor and a resetting transistor.

3. The semiconductor device according to claim 1 wherein said thin film transistor has a gate electrode over said channel formation region with a gate insulating therebetween.

4. A semiconductor device comprising:

at least one thin film transistor having a first crystalline semiconductor layer formed on an insulating surface, said first crystalline semiconductor layer including a channel formation region therein and at least one p-type impurity region as a source or drain region wherein the p-type impurity region contains both an n-type impurity and a p-type impurity; and

a photoelectric conversion element electrically connected to said thin film transistor, said photoelectric conversion element comprising;

a second n-type crystalline semiconductor layer formed on said insulating surface;

a third p-type crystalline semiconductor layer formed on said insulating surface; and

an amorphous semiconductor layer formed on and extending between the second n-type crystalline semiconductor layer and the third p-type crystalline semiconductor layer,

wherein the third p-type crystalline semiconductor layer contains the same impurities as said p-type impurity region of said one thin film transistor includes.

5. The semiconductor device according to claim 4 wherein said thin film transistor is selected from the group consisting of an amplifying transistor, a selecting transistor and a resetting transistor.

6. The semiconductor device according to claim 4 wherein said thin film transistor has a gate electrode over said channel formation region with a gate insulating therebetween.

7. A semiconductor device comprising:

at least one first thin film transistor having a first crystalline semiconductor layer formed on an insulating surface, said first crystalline semiconductor layer including a channel formation region therein and at least one p-type impurity region as a source or drain region wherein the p-type impurity region contains both an n-type impurity and a p-type impurity;

at least one second thin film transistor having a second crystalline semiconductor layer formed on the insulating surface, said second crystalline semiconductor layer including a channel formation region therein and at least one n-type impurity region as a source or drain region wherein the n-type impurity region contains an n-type impurity;

a photoelectric conversion element electrically connected to said first and second thin film transistors, said photoelectric conversion element comprising;

a third n-type crystalline semiconductor layer formed on said insulating surface;

a fourth p-type crystalline semiconductor layer formed on said insulating surface; and

an amorphous semiconductor layer formed on and extending between the third n-type crystalline semiconductor layer and the fourth p-type crystalline semiconductor layer,

wherein the third n-type crystalline semiconductor layer contains the same n-type impurity as said n-type impurity region of said second thin film transistor includes, and

wherein the fourth p-type crystalline semiconductor layer contains the same impurities as said p-type impurity region of said first thin film transistor includes.

8. The semiconductor device according to claim 7 wherein said photoelectric conversion element is directly connected to said first thin film transistor.

9. The semiconductor device according to claim 7 wherein said photoelectric conversion element is directly connected to said second thin film transistor.

10. The semiconductor device according to claim 7 wherein said first thin film transistor is selected from the group consisting of an amplifying transistor, a selecting transistor and a resetting transistor.

11. The semiconductor device according to claim 7 wherein said second thin film transistor is selected from the group consisting of an amplifying transistor, a selecting transistor and a resetting transistor.

12. The semiconductor device according to claim 7 wherein each of said first and second thin film transistors has a gate electrode over said channel formation region with a gate insulating therebetween.

13. A semiconductor device comprising:

at least one thin film transistor having a first crystalline semiconductor layer formed on an insulating surface, said first crystalline semiconductor layer including a channel formation region therein; and

a photoelectric conversion element electrically connected to said thin film transistor, said photoelectric conversion element comprising;

a second n-type crystalline semiconductor layer formed on said insulating surface;

a third p-type crystalline semiconductor layer formed on said insulating surface;

an insulating film formed over said second n-type crystalline semiconductor layer and said third p-type crystalline semiconductor layer wherein said insulating film has an opening to expose portions of the second n-type crystalline semiconductor layer and the third p-type crystalline semiconductor layer and a part of the insulating surface between the second n-type crystalline semiconductor layer and the third p-type crystalline semiconductor layer;

an amorphous semiconductor layer formed in the opening of the insulating film so that the amorphous semiconductor layer is in contact with both of the second n-type crystalline semiconductor layer and the third p-type crystalline semiconductor layer.

14. The semiconductor device according to claim 13 wherein said thin film transistor is selected from the group consisting of an amplifying transistor, a selecting transistor and a resetting transistor.

15. The semiconductor device according to claim 13 wherein said thin film transistor has a gate electrode over said channel formation region with a gate insulating therebetween.