Termination structure incorporating insulator in a trench

• US 6,825,510 B2
• Filed: 09/19/2002
• Issued: 11/30/2004
• Est. Priority Date: 09/19/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Probst, Dean
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/247,461
• Publication Number:
  US 20040056310A1
• Time in Patent Office: 803 Days
• Field of Search: 257/203, 257/204, 257/208, 257/401
• US Class Current: 257/208
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device 10 has increased breakdown voltage due to an oxide termination structure. A peripheral trench 58 is filled with a dielectric material, such as silicon dioxide. The trench extends below the P well 22 that includes the source 32. The electric field at the border to P well 22 and trench 60 turns upward toward the surface and passes through dielectric 60. A field plate 64 coves portions of the P well 22 and the dielectric 60.

Claims

1. A semiconductor device comprising:

a first layer of first conductivity type having an upper surface;

a diffusion region of second conductivity type formed along the surface end extending to a first depth within the first layer, said diffusion region forming a pn junction with the first layer;

a dielectric layer formed within the first layer and extending to at least the first depth, said dielectric layer positioned between the diffusion region and a peripheral region of the device, said dielectric layer in abutment with the diffusion region; and

a field plate disposed upon and in contact with at least a portion of each of the diffusion region and the dielectric layer.

2. The device of claim 1 wherein the dielectric layer is formed in a trench.

3. The device of claim 1 wherein the dielectric layer extends into the diffusion region beyond the first depth.

4. The device of claim 1 wherein the diffusion region is of a net P-type dopant concentration.

5. The device of claim 1 further including an active region comprising a MOSFET transistor with the field plate and dielectric layer formed in a region of the layer extending from the active region to the peripheral region of the device.

10. The device of claim 1, further comprising a field termination member disposed at least partially over and in contact with the dielectric layer and extending to a peripheral region of the device.

6. A semiconductor device with a field plate structure formed along an outer periphery thereof, comprising:

a semiconductor layer of predominately a first net conductivity type;

a diffusion region of a second net conductivity type formed in an upper surface of the semiconductor layer;

an insulator layer formed in contact with the diffusion region and extending into the semiconductor layer to at least the same depth as the diffusion region; and

a field plate disposed at least partially over and in contact with each of the diffusion region and the insulator layer.

7. The device of claim 6 wherein the diffusion region is of a net P-type dopant concentration.

8. The device of claim 6 further including an active region comprising a MOSFET transistor and wherein the field plate and dielectric layer are formed in a region of the layer extending from the active region to the outer periphery of the device.

9. The device of claim 6 wherein the insulator layer extends from the diffusion region toward the outer periphery and the field plate extends from the diffusion region toward the outer periphery and beyond the insulator.

11. A field plate termination structure for a semiconductor device, said semiconductor device having a first layer of a first conductivity type, said first layer having an upper surface, a diffusion region of second conductivity type formed along the upper surface and extending to a first depth within the first layer, said diffusion region forming a p-n junction with the first layer, said field plate termination structure comprising:

a dielectric layer formed at least partially within the first layer and extending to at least the first depth, said dielectric layer positioned between the diffusion region and a peripheral region of the device, said dielectric layer in abutment with the diffusion region;

a field plate member disposed upon and in contact with at least a portion of each of the diffusion region and the dielectric layer; and

a field termination member disposed between said field plate member and the peripheral region.

12. The field plate termination of claim 11, wherein said field termination member is disposed at least partially over and in contact with the dielectric layer and extends to the peripheral region.

13. The field plate termination of claim 11, wherein said field termination member comprises at least one field plate ring disposed at least partially within the first layer.