High-voltage semiconductor component

• US 6,825,514 B2
• Filed: 06/06/2003
• Issued: 11/30/2004
• Est. Priority Date: 11/09/2001
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG
• Inventors: Strack, Helmut, Rueb, Michael, Deboy, Gerald, Weber, Hans Martin, Ahlers, Dirk
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/455,858
• Publication Number:
  US 20030232477A1
• Time in Patent Office: 543 Days
• Field of Search: 257/285, 257/287
• US Class Current: 257/285
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A process for manufacturing of a semiconductor device comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode, the side of the zone of the second conductivity type facing the drain zone forming a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, areas of the first and second conductivity type nested in one another, comprises the step of:

varying in individual semiconductor layers, by doping, the degree of compensation in the regions of the second conductivity type.

Claims

1. Process for manufacturing of a semiconductor device comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode, the side of the zone of the second conductivity type facing the drain zone forming a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, areas of the first and second conductivity type nested in one another, comprising the step of:

varying in individual semiconductor layers, by doping, the degree of compensation in the areas of the second conductivity type.

2. Process according to claim 1, further comprising the step of:

varying in individual semiconductor layers, by doping, the degree of compensation in the areas of the first conductivity type.

3. Process for manufacturing of a semiconductor device comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode, the side of the zone of the second conductivity type facing the drain zone forming a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, areas of the first and second conductivity type nested in one another, comprising the step of:

varying in individual semiconductor layers, by doping, the degree of compensation in the areas of the first conductivity type.

4. Process according to claim 3, further comprising the step of:

varying in individual semiconductor layers, by doping, the degree of compensation in the areas of the second conductivity type.

5. Process for manufacturing of a semiconductor device comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode, the side of the zone of the second conductivity type facing the drain zone forming a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, areas of the first and second conductivity type nested in one another, comprising the step of:

varying in individual semiconductor layers, by doping, the degree of compensation in the areas of the first conductivity type, and

varying in individual semiconductor layers, by doping, the degree of compensation in the areas of the second conductivity type.