Multichip wafer level packages and computing systems incorporating same

• US 6,825,553 B2
• Filed: 09/05/2003
• Issued: 11/30/2004
• Est. Priority Date: 08/27/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Neo, Yong Loo, Boon, Suan Jeung, Zhou, Wei, Low, Siu Waf, Chua, Swee Kwang, Chia, Yong Poo, Eng, Meow Koon, Huang, Suangwu
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US10/656,352
• Publication Number:
  US 20040046250A1
• Time in Patent Office: 452 Days
• Field of Search: 257/691, 257/723, 257/701, 257/713, 257/773, 257/774, 257/750
• US Class Current: 257/691
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate'"'"'s back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

Claims

1. A semiconductor device package, comprising:

a plurality of semiconductor dice, each semiconductor die of the plurality having a back surface, an active surface and a plurality of signal connection devices on the active surface;

a substrate having an attachment surface, an opposing surface and a plurality of openings formed therethrough, wherein each of the plurality of signal connection devices is positioned in one of the plurality of openings and the active surfaces of the plurality of semiconductor dice are adhered to the attachment surface of the substrate permitting exposure of the plurality of signal connection devices through the plurality of openings; and

a molding layer disposed over the attachment surface of the substrate and the back surfaces of the plurality of semiconductor dice.

2. The semiconductor device package of claim 1, further comprising:

a first dielectric layer upon the opposing surface of the substrate; and

a plurality of openings in the first dielectric layer exposing the plurality of signal connection devices therethrough.

3. The semiconductor device package of claim 2, wherein the substrate includes a silicon wafer.

4. The semiconductor device package of claim 2, wherein the plurality of signal connection devices is selected from the group consisting of gold stud bumps, copper stud bumps, and plated stud bumps.

5. The semiconductor device package of claim 2, wherein each of the plurality of openings exhibits a depth which is at least as great as or greater than a height of each of the plurality of signal connection devices.

6. The semiconductor device package of claim 2, further comprising a layer of die attach material disposed between and adhering the active surface of each of the plurality of semiconductor dice and the attachment surface of the substrate.

7. The semiconductor device package of claim 6, wherein the layer of die attach material comprises an epoxy material.

8. The semiconductor device package of claim 6, wherein the layer of die attach material comprises a polyimide material.

9. The semiconductor device package of claim 6, wherein the layer of die attach material comprises benzocyclobutene.

10. The semiconductor device package of claim 6, wherein the layer of die attach material exhibits a dielectric constant of up to about three.

11. The semiconductor device package of claim 2, wherein the molding layer comprises a material which is capable of withstanding a temperature of up to about 300°

C. without substantial degradation thereof.

12. The semiconductor device package of claim 2, further comprising:

a first circuit layer over the first dielectric layer electrically connected to the plurality of signal connection devices;

at least one additional dielectric layer, having at least one additional plurality of openings formed therethrough; and

at least one additional circuit layer over the at least one additional dielectric layer electrically coupled with the first circuit layer;

an outermost dielectric layer having a plurality of holes formed therethrough, the outermost dielectric layer being disposed over the at least one additional circuit layer; and

a plurality of conductive bumps disposed in the plurality of holes of the outermost dielectric layer and electrically coupled with the at least one additional circuit layer.

13. A memory device comprising:

a carrier substrate;

a plurality of electrical contacts coupled with electrical circuitry formed in the carrier substrate; and

at least one semiconductor device package coupled with the electrical circuitry in the carrier substrate, the at least one semiconductor device package comprising;

a plurality of semiconductor dice, each semiconductor die of the plurality having a back surface, an active surface and a plurality of signal connection devies on the active surface;

a substrate having an attachment surface, an opposing surface and a plurality of openings formed therethrough, wherein each of the plurality of signal connection devices is positioned in one of the plurality of openings and the active surfaces of the plurality of semiconductor dice are adhered to the attachment surface of the substrate permitting exposure of the plurality of signal connection devices through the plurality of openings; and

a molding layer disposed over the attachment surface of the substrate and the back surfaces of the plurality of semiconductor dice.

14. A computing system comprising:

a carrier substrate;

a processor operably coupled to the carrier substrate;

at least one input device operably coupled with the carrier substrate;

at least one output device operably coupled with the carrier substrate; and

a memory device operably coupled to the carrier substrate, the memory device including at least one semiconductor device package, the at least one semiconductor device package comprising;

a plurality of semiconductor dice, each semiconductor die having a back surface, an active surface and a plurality of signal connection devices on the active surface;

a substrate having an attachment surface, an opposing surface and a plurality of openings formed therethrough, wherein each of the plurality of signal connection devices is positioned in one of the plurality of openings and the active surfaces of the plurality of semiconductor dice are adhered to the attachment surface of the substrate permitting exposure of the plurality of signal connection devices through the plurality of openings; and

a molding layer disposed over the attachment surface of the substrate and the back surfaces of the plurality of semiconductor dice.

15. A semiconductor device package comprising:

a plurality of semiconductor dice, each semiconductor die of the plurality having a back surface, an active surface and a plurality of signal connection devices on the active surface;

a substrate having a plurality of cavities formed in a first surface of the substrate, wherein each semiconductor die of the plurality is disposed in one of the plurality of cavities with the back surface of each semiconductor die facing the base of its respective one of the plurality of cavities;

a first dielectric layer disposed upon the first surface of the substrate and upon the active surface of each of the plurality of semiconductor dice; and

a plurality of openings in the first dielectric layer exposing the plurality of signal connection devices.

16. The semiconductor device package of claim 15, where the substrate comprises a silicon wafer.

17. The semiconductor device package of claim 15, wherein the plurality of signal connection devices comprises bond pads.

18. The semiconductor device package of claim 15, wherein each of the plurality of cavities exhibits a same depth which is at least equal to or greater than a height of each the plurality of semiconductor dice.

19. The semiconductor device package of claim 15, further comprising a layer of die attach material disposed in the plurality of cavities and adhering the back surface of each of the plurality of semiconductor dice to the base of its respective one of the plurality of cavities.

20. The semiconductor device package of claim 19, wherein the layer of die attach material comprises an epoxy material.

21. The semiconductor device package of claim 19, where the layer of die attach material comprises a polyimide material.

22. The semiconductor device package of claim 19, wherein the layer of die attach material comprises benzocyclobutene.

23. The semiconductor device package of claim 19, wherein the layer of die attach material further comprises a material exhibiting a dielectric constant of up to about three.

24. The semiconductor device package of claim 15, further comprising:

a first circuit layer over the first dielectric layer electrically connected to the plurality of signal connection devices;

at least one additional dielectric layer, having at least one additional plurality of openings formed therethrough; and

at least one additional circuit layer over the at least one additional dielectric layer electrically coupled with the first circuit layer;

an outermost dielectric layer having a plurality of holes formed therethrough, the outermost dielectric layer being disposed over the at least one additional circuit layer; and

a plurality of conductive bumps disposed in the plurality of holes of the outermost dielectric layer and electrically coupled with the at least one additional circuit layer.

25. A memory device comprising:

a printed circuit board;

a plurality of electrical contacts coupled with electrical circuitry formed in the printed circuit board; and

at least one semiconductor device package coupled with the electrical circuitry in the printed circuit board, the at least one semiconductor device package comprising;

a plurality of semiconductor dice, each semiconductor die of the plurality having a back surface, an active surface and a plurality of signal connection devcies on the active surface;

a substrate having a plurality of cavities formed in a first surface of the substrate, wherein each semiconductor die of the plurality is disposed in one of the plurality of cavities with the back surface of each semiconductor die facing the base of its respective one of the plurality of cavities;

a first dielectric layer disposed upon the first surface of the substrate and upon the active surface of each of the plurality of semiconductor dice; and

a plurality of openings in the first dielectric layer exposing the plurality of signal connection devices.

26. A computing system comprising:

a printed circuit board;

a processor operably coupled to the printed circuit board;

at least one input device operably coupled with the printed circuit board;

at least one output device operably coupled with the printed circuit board; and

a memory device operably coupled to the printed circuit board, the memory device including at least one semiconductor device package, the at least one semiconductor device package comprising;

a plurality of semiconductor dice, each semiconductor die of the plurality having a back surface, an active surface and a plurality of signal connection devices on the active surface;

a substrate having a plurality of cavities formed in a first surface thereof, wherein each semiconductor die of the plurality is disposed in one of the plurality of cavities with the back surface of each semiconductor die facing the base of its respective one of the plurality of cavities;

a first dielectric layer disposed upon the first surface of the substrate and upon the active surface of each of the plurality of semiconductor dice; and

a plurality of openings in the first dielectric layer exposing the plurality of signal connection devices.