Granularity memory column access

• US 6,825,841 B2
• Filed: 09/07/2001
• Issued: 11/30/2004
• Est. Priority Date: 09/07/2001
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Warmke, Richard E., Hampel, Craig E., Ware, Frederick A.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/949,464
• Publication Number:
  US 20030052885A1
• Time in Patent Office: 1,180 Days
• Field of Search: 345/519, 345/533, 345/541-2, 345/559-561, 345/564-572, 345/536, 345/501, 345/530, 345/531, 345/545, 365/230.01, 365/230.06, 365/230.08, 711/200, 711/202, 711/211
• US Class Current: 345/519
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially different column addresses depending on the needs of the device utilizing the memory. For example, the column addresses might be based on a received CAS address and an accompanying offset. This allows data access at alignments that do not necessarily correspond to CAS alignments. The technique is utilized in conjunction with graphics systems in which tiling is used. In systems such as this, memory offsets are specified in terms of pixel columns and rows. The technique is also used in conjunction with a router such as a TCP/IP router, in which individual packets are aligned at CAS boundaries. In this situation, the decoder logic is alternatively configurable to allow access of either an information packet or a plurality of packet headers during a single memory access cycle.

Claims

1. A memory device comprising:

an integrated circuit, the integrated circuit comprising;

a plurality of storage units;

a data I/O path through which groups of the storage units arc accessed in parallel; and

selection logic configured to select groups of the storage units for parallel access Through the data I/O path;

wherein the selection logic is configurable to select a first group of storage units that includes a particular one of the storage units, and to select a second, different group of storage units that also includes the particular one of the storage units.

2. A memory device as recited in claim 1, wherein the selection logic is also configurable to select mutually exclusive groups of the storage units.

3. A memory device as recited in claim 1, wherein the plurality of storage units are arranged in a plurality of arrays, and wherein each group includes at least one storage unit from each array.

4. A memory device as recited in claim 1, wherein the selection logic is configurable by means of a received offset value.

5. A memory device as recited in claim 1, wherein the selection logic is configurable by means of a received mode command.

6. A memory device as recited in claim 1, wherein the selection logic is configurable by means of a received CAS command.

7. A memory device as recited in claim 1, wherein the selection logic is configurable by means of a received address command.

8. A memory device as recited in claim 1, further comprising a storage register that is programmable to configure the selection logic.

9. A memory device comprising:

a plurality of memory cells;

a data I/O path through which groups of the memory cells are accessed in parallel; and

selection logic configured to select memory cells for parallel access through the data I/O path;

wherein the selection logic is configurable to allow selection of overlapping groups of the memory cells for parallel access through the data I/O path; and

wherein the plurality of memory cells, the data I/O path, and the selection logic are part of a single integrated circuit.

10. A memory device as recited in claim 9, wherein the selection logic is also configurable to allow selection of mutually exclusive groups of the memory cells.

11. A memory device as recited in claim 9, wherein the selection logic is responsive to an address specification to select the overlapping groups of memory cells.

12. A memory device as recited in claim 9, wherein the selection logic is responsive to an address and at least one offset to select the overlapping groups of memory cells.

13. A memory device as recited in claim 9, wherein the selection logic is responsive to an address and at least one off set to select the overlapping groups of memory cells, wherein the address and at least one offset are received during a memory access operation.

14. A memory device as recited in claim 9, wherein the selection logic is responsive to an address and at least one offset to select the overlapping groups of memory cells, wherein said at least one offset is stored in a register prior to a memory access operation.

15. A memory device as recited in claim 9, wherein the selection logic is responsive to an address and at least one offset to select the overlapping groups of memory cells, wherein said at least one offset is stored in the memory device prior to a memory access operation, and wherein the memory device is programmable to indicate whether said at least one offset is to be used in conjunction with a received memory address during a memory access operation.

16. A memory device as recited in claim 9, wherein the selection logic is responsive to an address and a previously stored offset to select the overlapping groups of memory cells.

17. A memory device as recited in claim 9, wherein the selection logic is responsive to an address and an offset to select the overlapping groups of memory cells, the offset being specified relative to a linear sequence of the memory cells.

18. A memory device as recited in claim 9, wherein the selection logic is responsive to an address and an offset to select the overlapping groups of memory cells, the offset being specified in terms of graphics tile columns.

19. A memory device as recited in claim 9, wherein the selection logic is responsive to an address and an offset to select the overlapping groups of memory cells, the offset being specified in terms of graphics tile rows.

20. A memory device as recited in claim 9, wherein the selection logic is responsive to an address, a horizontal offset, and a vertical offset to select the overlapping groups of memory cells, the horizontal offset being specified in terms of graphics tile columns and the vertical offset being specified in terms of graphics tile rows.

21. A memory device as recited in claim 9, the selection logic comprising a plurality of lane decoders, wherein at least two of the lane decoders receive potentially different decoder addresses.

22. A graphic system comprising:

a memory device as recited in claim 9;

a graphics controller that is configured to store graphics information corresponding to rectangular tiles in the groups of memory cells.

23. A memory device comprising:

a plurality of memory cells;

a plurality of parallel data I/O lanes;

I/O lane decoders associated respectively with the data I/O lanes;

decoder logic that is responsive to a memory address and to one or more adjustment values to calculate addresses for the individual I/O lane decoders during a memory access cycle, wherein at least two of the calculated addresses are allowed to differ from each other;

wherein the I/O lane decoders are responsive to the calculated addresses to select memory cells for access through the data I/O lanes during memory access cycle.

24. A memory device as recited in claim 23, wherein the adjustment values allow selection of overlapping groups of memory cells for access through the data I/O lanes during different memory access cycles.

25. A memory device as recited in claim 23, wherein memory device is configured to receive the one or more adjustment values during the memory access cycle.

26. A memory device as recited in claim 23, wherein memory device is configured to receive the one or more adjustment values prior to the memory access cycle.

27. A memory device as recited in claim 23, wherein the one or more received adjustment values comprise a lane offset value.

28. A memory device as recited in claim 23, wherein each data I/O lane is a single byte in width.

29. A memory device as recited in claim 23, wherein each data I/O lane is multiple bytes in width.

30. A memory device as recited in claim 23, further comprising:

a storage register containing one or more tiling parameters;

wherein the decoder logic is further responsive to the one or more tiling parameters to calculate the addresses.

31. A memory device as recited in claim 23, wherein the one or more received adjustment values comprise pixel offsets specified relative to graphics tiles.

32. A graphics system comprising:

a memory device as recited in claim 23;

a graphics controller tat is configured to store tiles of graphics information in the memory cells of the memory device;

wherein the adjustment values are received from the graphics controller and are specified in terms of horizontal or vertical pixel offsets relative to the rectangular tiles of graphics information.

33. A graphics system comprising:

a memory device as recited in claim 23;

a graphics controller that is configured to store tiles of graphics information in the memory cells of the memory device;

wherein the adjustment values are received from the graphics controller and are specified in terms of horizontal or vertical pixel offsets relative to the rectangular tiles of graphics information;

the memory device further comprising a storage register containing one or more tiling parameters that are programmable by the graphics controller;

wherein the decoder address logic is further responsive to the one or more tiling parameters to calculate the addresses for the individual I/O lane decoders.

34. A memory device as recited in claim 23, wherein during the memory access cycle, a plurality of columns from the plurality of memory cells are accessed in parallel.

35. A memory device as recited in claim 23, wherein the memory access cycle is a single CAS access cycle.

36. An integrated circuit comprising:

a plurality of memory arrays having memory cell columns;

a plurality of parallel data I/O lanes corresponding respectively to the memory arrays;

column selection logic tat is configurable to select potentially different memory cell columns of the respective memory arrays for parallel access through the data I/O lanes in a single memory access cycle.

37. An integrated circuit as recited in claim 36, wherein the column selection logic is also configurable to select the same memory cell columns of each of the respective memory arrays for parallel access through the data I/O lanes.

38. An integrated circuit as recited in claim 36, wherein the column selection logic is responsive to a memory address and to one or more adjustment values to select the potentially different memory cell columns of the respective memory arrays.

39. An integrated circuit as recited in claim 36, wherein the column selection logic is responsive to a memory address and to a lane offset value to select the potentially different memory cell columns of the respective memory arrays.

40. An integrated circuit as recited in claim 36, wherein each data I/O lane is a single byte in width.

41. An integrated circuit as recited in claim 36, wherein each data I/O lane is multiple bytes in width.

42. An integrated circuit as recited in claim 36, wherein the column selection is responsive to memory address and to one or more adjustment values to select the potentially different memory cell columns of the respective memory arrays, wherein the memory address and adjustment values are received during a memory access command.

43. An integrated circuit as recited in claim 36, wherein the column selection logic is responsive to a memory address and to one or more adjustment values to select the potentially different memory cell columns of the respective memory arrays, wherein the memory address is received during a memory access commend and the adjustment values are received prior to the memory access command.

44. An integrated circuit as recited in claim 36, further comprising:

a storage register containing one or more filing parameters; and

wherein the column selection logic is responsive to a memory address, one or more offset values, and the one or more tiling parameters to select the potentially different memory cell columns of the respective memory arrays.

45. An integrated circuit as recited in claim 36, wherein the column selection logic is responsive to a memory address and to an adjustment value to select the potentially different memory cell columns of the respective memory arrays, wherein the received adjustment value comprises a pixel offset specified relative to an array of graphics tiles.

46. A graphics system comprising:

an integrated circuit as recited in claim 36;

a graphics controller that is configured to store graphics information corresponding to a rectangular tile of pixels in the memory cells of the integrated circuit.

47. A graphics system comprising:

an integrated circuit as recited in claim 36;

a graphics controller that is configured to store graphics information corresponding to a rectangular tile of pixels in the memory cells of the integrated circuit;

the integrated circuit further comprising a storage register containing one or more tiling parameters that are programmable by the graphics controller;

wherein the column selection logic is responsive to a memory address received from the graphics controller, one or more offset values received from the graphics controller, and the one or more tiling parameters to select the potentially different memory cell columns of the respective memory arrays.

48. A packet router comprising:

an integrated circuit as recited in claim 36;

packet routing logic that stores information packets in the integrated circuit, the information packets having headers that specify packet routing information; and

wherein the column selection logic selects the potentially different memory cell columns so that a plurality of packet headers are accessed in parallel through the data I/O lanes.

49. An integrated circuit as recited in claim 36, wherein during the single memory access cycle, a plurality of the memory cell columns are accessed in parallel.

50. An integrated circuit as recited in claim 36, wherein the single memory access cycle is a single CAS access cycle.

51. A memory device that is configurable for use as graphics memory in which memory storage units represent rectangular tiles of graphics pixels, the memory device including an integrated circuit, the integrated circuit comprising:

a plurality of memory storage units configured to store graphics data;

a plurality of parallel data I/O lanes that collectively transfer memory data corresponding to a rectangular tile of graphics pixels during a memory access cycle;

selection logic that is responsive to a received memory address and to one or more offset values to select storage units corresponding to tiles of graphics pixels for parallel access through the data I/O lanes;

wherein the selection logic is configurable to allow selection of overlapping tiles of the memory cells for parallel access trough the data I/O path.

52. A memory device as recited in claim 51, wherein the selection logic is configurable to allow selection of non-overlapping tiles of the memory cells for parallel access through the data I/O path.

53. A memory device as recited in claim 51, wherein each data I/O lane is a single byte in width.

54. A memory device as recited in claim 51, wherein each data I/O lane is multiple bytes in width.

55. A memory device as recited in claim 51, wherein:

each rectangular tile has a horizontal pixel dimension, and;

the one or more offset values comprise a horizontal pixel offset.

56. A memory device as recited in claim 51, wherein:

each rectangular tile has a horizontal pixel dimension, and;

the one or more offset values comprise a horizontal pixel offset value that is not constrained to multiples of the horizontal pixel dimension.

57. A memory device as recited in claim 51, wherein:

each rectangular tile has a vertical pixel dimension, and;

the one or more offset values comprise a vertical pixel offset.

58. A memory device as recited in claim 51, wherein:

each rectangular tile has a vertical pixel dimension, and;

the one or more offset values comprise a vertical pixel offset that is not constrained to multiples of the vertical pixel dimension.

59. A memory device as recited in claim 51, wherein:

each rectangular tile has a horizontal pixel dimension and a vertical pixel dimension;

the one or more offset values comprise a horizontal pixel offset and a vertical pixel offset.

60. A memory device as recited in claim 51, wherein:

each rectangular file has a horizontal pixel dimension and a vertical pixel dimension;

the one or more offset values comprise a horizontal pixel offset that is not constrained to multiples of the horizontal pixel dimension and a vertical pixel offset tat is not constrained to multiples of the vertical pixel dimension.

61. A memory device as recited in claim 51, further comprising a storage register containing one or more tiling parameters, wherein:

each rectangular file has a vertical pixel dimension, and;

the one or more offset values comprise a vertical pixel offset that is not constrained to multiples of the vertical pixel dimension;

wherein the selection logic is further responsive to the one or more tiling parameters to select storage units corresponding to tiles of graphics pixels.

62. A memory device that is configurable for use as graphics memory in which memory storage units represent files of graphics pixels having at least two pixel dimensions, comprising:

a plurality of arrays of memory storage units configured to store graphics memory data;

a plurality of parallel data I/O lanes corresponding respectively to the arrays of memory storage units, wherein the parallel data I/O lanes collectively transfer memory data corresponding to a rectangular tile of graphics pixels during a memory access cycle;

lane decoders associated respectively with the data I/O lanes and the arrays of memory storage units;

address specification logic that is responsive to a received memory address and to one or more dimensional offset values to calculate decoder addresses for the lane decoders during a `memory access cycle, wherein at least two of the decoder addresses are different from each other;

wherein the lane decoders are responsive to the address specifications to select memory storage units corresponding to a file of graphics pixels;

wherein the one or more dimensional offset values are not restricted to multiples of the pixel dimensions.

63. A memory device as recited in claim 62, wherein each data I/O lane is a single byte in width.

64. A memory device as recited in claim 62, wherein each data I/O lane is multiple bytes in width.

65. A memory device as recited in claim 62, wherein the one or more dimensional offset values comprise a horizontal pixel offset value and a vertical pixel offset value.

66. A memory device as recited in claim 62, wherein:

the one or more dimensional offset values comprise a horizontal pixel offset value and a vertical pixel offset value; and

the horizontal pixel offset value and the vertical pixel offset value are not constrained to multiples of the two pixel dimensions.

67. A memory device as recited in claim 62, further comprising a storage register containing one or more tiling parameters, wherein:

wherein the address specification logic is further responsive to the one or more tiling parameters to calculate the different decoder addresses.

68. A memory device as recited in claim 62, wherein during the memory access cycle, a plurality of columns from the plurality of arrays of memory storage units are accessed in parallel.

69. A memory device as recited in claim 62, wherein the memory access cycle is a single CAS access cycle.

70. A memory device comprising:

a plurality of arrays of memory storage units;

at least one row decoder that selects at least one row of memory storage units across the plurality of arrays of memory storage units;

a plurality of column decoders tat select columns of the plurality of arrays of memory storage units responsive to a plurality of column addresses, each respective column decoder of the plurality of column decoders associated with a respective array of memory storage units of the plurality of arrays of memory storage units; and

address specification logic tat is responsive to at least one received memory address and to one or more adjustment values to calculate the plurality of column addresses for the plurality of column decoders, wherein at least two of the plurality of column addresses are different from each other;

wherein respective column decoders of the plurality of column decoders receive respective column addresses of the plurality of column addresses.

71. A memory device as recited in claim 70, further comprising:

a plurality of data I/O lanes corresponding respectively to the plurality of column decoders and coupled thereto.

72. A memory device as recited in claim 70, wherein each memory storage unit comprises a single byte or multiple bytes.

73. A memory device as recited in claim 70, further comprising:

a storage register that is programmable to configure the address specification logic.

74. A memory device as recited in claim 70, further comprising:

a plurality of column address communication channels that couple the address specification logic to respective column decoders of the plurality of column decoders.

75. A memory device as recited in claim 70, wherein the single respective column decoders receive the respective column addresses during a single memory access cycle.

76. A memory device as recited in claim 75, wherein to single memory access cycle comprises a single CAS access cycle.

77. A memory device as recited in claim 75, wherein during the single memory access cycle, a plurality of columns from the plurality of arrays of memory storage units are accessed in parallel via to plurality of column decoders.

78. A memory device as recited in claim 70, wherein the address specification logic is configurable using at least one of a received address command, a received CAS command, a received mode command, or the one or more adjustment values.

79. A memory device as recited in claim 70, wherein the one or more adjustment values are specified in terms of graphics file rows or graphics tiles columns.

80. A memory device as recited in claim 70, wherein the one or more adjustment values allow selection of overlapping groups of memory storage units for access through the plurality of column decoders during different memory access cycles.

81. A memory device as recited in claim 70, wherein (i) the at least one received memory address and the one or more adjustment values are received during a memory access command or (ii) the at least one received memory address is received during a memory access command and the one or more adjustment values are received prior to the memory access command.

82. A memory device as recited in claim 70, wherein the one or more adjustment values comprise a horizontal pixel offset value and/or a vertical pixel offset value.

83. A memory device as recited in claim 70, wherein the one or more adjustment values comprise at least one lane offset value.