Twin P-well CMOS imager
First Claim
Patent Images
1. An imaging device comprising:
- at least one pixel circuit including;
a photosensitive device within a substrate for accumulating photo-generated charge;
a floating diffusion node formed in said substrate for receiving and storing charges from said photosensitive device;
at least one transistor formed on said substrate having a first voltage threshold which is used in operating said pixel;
an output node for providing a pixel signal; and
a readout circuit comprising at least one transistor which is formed on said substrate used in operation of said readout circuit, said at least one transistor being coupled to receive a signal from said pixel output node and having a second voltage threshold which is lower than said first voltage threshold, said at least one transistor providing an output signal based on a signal received from said pixel circuit; and
a substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage.
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Abstract
A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in the doped area. The invention also provides a CMOS imager where a photodetector sensor array is formed in a first p-well and readout logic is formed in a second p-well. The first p-well can be selectively doped to optimize cross-talk, collection efficiency and transistor leakage, thereby improving the quantum efficiency of the sensor array while the second p-well can be selectively doped and/or biased to improve the speed and drive of the readout circuitry.
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Citations
63 Claims
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1. An imaging device comprising:
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at least one pixel circuit including;
a photosensitive device within a substrate for accumulating photo-generated charge;
a floating diffusion node formed in said substrate for receiving and storing charges from said photosensitive device;
at least one transistor formed on said substrate having a first voltage threshold which is used in operating said pixel;
an output node for providing a pixel signal; and
a readout circuit comprising at least one transistor which is formed on said substrate used in operation of said readout circuit, said at least one transistor being coupled to receive a signal from said pixel output node and having a second voltage threshold which is lower than said first voltage threshold, said at least one transistor providing an output signal based on a signal received from said pixel circuit; and
a substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An imaging device comprising:
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an array of pixels, each pixel including;
a photosensitive device formed in a substrate for causing accumulation of the photo-generated charge in an underlying portion of said substrate;
a floating diffusion node formed in said substrate for receiving and storing charges from said photosensitive device;
at least one transistor formed on said substrate having a first voltage threshold which is used in operating said pixel;
an output node for providing a pixel signal; and
a readout circuit comprising at least one transistor which is formed on said substrate used in operation of said readout circuit, said at least one transistor being coupled to receive a signal from said pixel output node and having a second voltage threshold which is lower than said first voltage threshold, said at least one transistor providing an output signal based on a signal received from said pixel circuit; and
at least one substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. An imaging system for generating an output signal based on an applied image, the imaging system comprising:
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a plurality of pixels arranged into an array of rows and columns, each pixel including a photosensor, a floating diffusion node for storing charges from said photosensor, and at least one transistor formed on said substrate having a first voltage threshold that is used in operating said pixel;
a plurality of readout circuits, each readout circuit being connected to the respective pixels in a column, each readout circuit comprising at least one transistor for receiving signals from the pixels of a column and having a second voltage threshold which is lower than said first voltage threshold, said readout circuit transistor being operable to store signals received from a pixel of a respective column and to provide a pixel output signal;
at least one substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage; and
a row decoder having a plurality of control lines connected to the sensor array, each control line being connected to the pixel sensors in a respective row, wherein the row decoder is operable to activate the pixels in a row by row fashion. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor and including;
a substrate;
at least one pixel circuit including;
a photosensitive device within a substrate for accumulating photo-generated charge;
a floating diffusion node formed in said substrate for receiving and storing charges from said photosensitive device;
at least one transistor formed on said substrate having a first voltage threshold which is used in operating said pixel;
an output node for providing a pixel signal; and
a readout circuit comprising at least one transistor which is formed on said substrate used in operation of said readout circuit, said at least one transistor being coupled to receive a signal from said pixel output node and having a second voltage threshold which is lower than said first voltage threshold, said at least one transistor providing an output signal based on a signal received from said pixel circuit; and
a substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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54. A method fabricating a CMOS imager circuit, said method comprising:
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forming a pixel circuit having at least one transistor having a first voltage threshold;
forming a readout circuit coupled to receive an output signal of said pixel circuit and having at least one transistor having a second voltage threshold which is lower than said first voltage threshold; and
forming a charge pump for biasing a substrate on which said pixel circuit and readout circuit are formed.
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55. A method fabricating a CMOS imager circuit, said method comprising:
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forming a substrate of a first conductivity;
forming a first well of said first conductivity in said substrate, said first well including a pixel area; and
forming a second well of said first conductivity and a third well of a second conductivity, said second and third well being in a peripheral logic area; and
forming a voltage pump for biasing a substrate containing said pixel area and peripheral logic area. - View Dependent Claims (56, 57, 58, 59, 60, 61, 62, 63)
forming a reset transistor having a first voltage threshold for resetting a floating diffusion node to a predetermined voltage;
forming a transfer transistor having said first voltage threshold for transferring charge collected by said photosensitive charge collection area to a floating diffusion node;
forming a source follower transistor having said first voltage threshold for transferring charge from floating diffusion node; and
forming a row select transistor having said first voltage threshold for selectively gating an output produced by said source follower transistor.
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57. The method of claim 56, further comprising forming a readout circuit for receiving a signal from said pixel in said peripheral logic area.
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58. The method of claim 57, wherein said readout circuit includes at least one transistor having a second voltage threshold which is less than said first voltage threshold.
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59. The method of claim 55, wherein said deep well is doped with boron implanted at a dose of about 1.0×
- 1011 ions/cm2 to about 1.0×
1013 ions/cm2.
- 1011 ions/cm2 to about 1.0×
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60. The method of claim 55, wherein said first shallow well is doped with boron implanted at a dose of about 5.0×
- 1011 ions/cm2 to about 5.0×
1013 ions/cm2.
- 1011 ions/cm2 to about 5.0×
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61. The method of claim 55, wherein said first shallow well is formed within said second shallow well.
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62. The method of claim 55, wherein said first conductivity is p-type and said second conductivity is n-type.
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63. The method of claim 55, wherein said first conductivity is n-type and said second conductivity is p-type.
Specification