TFT array substrate, and liquid crystal display device using the same

• US 6,825,907 B2
• Filed: 02/14/2002
• Issued: 11/30/2004
• Est. Priority Date: 06/27/2000
• Status: Expired due to Term

• Current Assignee: Trivale Technologies, LLC (Vector Capital Corporation)
• Original Assignee: Kabushiki Kaisha Advanced Display
• Inventors: Yamaguchi, Takehisa, Nakagawa, Naoki, Hashiguchi, Takafumi
• Primary Examiner(s): Nguyen, Dung T.
• Application Number:
  US10/049,715
• Publication Number:
  US 20020113916A1
• Time in Patent Office: 1,020 Days
• Field of Search: 349/139, 349/42, 349/43
• US Class Current: 349/139
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Abstract

The widths of those portions of a semiconductor layer 5 and a drain line 6a overlapping with it which cross an edge line of a gate electrode 2 are made smaller than the channel width of a thin-film transistor. With this measure, the overlap area of the gate electrode 2 and a drain electrode 6 is reduced. As a result, a variation of the above overlap area due to alignment errors in a photolithography apparatus used in patterning the gate lines 2, the drain electrodes 6, and source electrodes 7 can be reduced and the frequency of occurrence of display defects can be decreased.

Claims

1. A TFT array substrate comprising;

a plurality of gate lines formed on an insulative substrate, each of the gate lines includes a gate electrode,

a plurality of source lines crossing the gate lines, each of the source lines includes a source electrode,

a semiconductor layer formed on the gate electrodes with a gate insulating film interposed in between,

a thin-film transistor formed by the source electrode and a drain electrode, the source electrode and a drain electrode are connected to the semiconductor layer, and

a pixel electrode connected to a drain line extending from the drain electrode,

wherein a width of a crossing portion of the semiconductor layer and a width of a crossing portion of the drain line overlapping with the semiconductor layer that cross an edge line of the gate electrode are made smaller than a width of the drain electrode that is equal to a channel width of the thin-film transistor.

2. The TFT array substrate according to claim 1, wherein the drain electrode and the drain line have portions that are located over the gate electrode and do not coextend with the semiconductor layer.

3. A liquid crystal display device characterized in that a liquid crystal is interposed between the TFT array substrate according to claim 1 and a counter electrode substrate having a transparent electrode.