Interleaved wordline architecture

• US 6,826,069 B2
• Filed: 12/18/2003
• Issued: 11/30/2004
• Est. Priority Date: 03/14/2001
• Status: Expired due to Fees

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Atmos Coporation (Peraso, Inc.)
• Inventors: Kurjanowicz, Wlodek, Kwok, David Chi Wing
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Pham, Ly Duy
• Application Number:
  US10/737,825
• Publication Number:
  US 20040125636A1
• Time in Patent Office: 348 Days
• Field of Search: 365/63, 365/51, 365/230.05, 365/190, 365/69
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance. Hence the memory cell architecture of the present invention occupies less area, and operates with faster speed than memory cell architectures of the prior art.

Claims

1. A folded bitline memory array comprising:

a plurality of pairs of memory cells arranged in a substantially linear row, each said pairs of memory cells being coupled to a complementary folded bitline;

a plurality of logically different wordline segments coupled to each said pairs of memory cells; and

a plurality of conducting wordlines each coupled to logically identical wordline segments.

2. The folded bitline memory array of claim 1, wherein a number of wordline segments of the substantially linear row of pairs of memory cells are each coupled to 2 memory cells.

3. The folded bitline memory array of claim 1, wherein a number of wordline segments of the substantially linear row of pairs of memory cells are each coupled to 4 memory cells.

4. The folded bitline memory array of claim 1, wherein a number of wordline segments of the substantially linear row of pairs of memory cells are each coupled to 8 memory cells.

5. The folded bitline memory array of claim 1, wherein the wordline segments are formed of polysilicon.

6. The folded bitline memory array of claim 1, wherein the wordline segments are formed of metal.

7. The folded bitline memory array of claim 1, wherein the wordline segments are formed of low resistivity conductor materials.

8. The folded bitline memory array of claim 1, wherein each of said pairs of memory cells in the substantially linear row are adjacent to each other.

9. The folded bitline memory array of claim 1, wherein the memory cells of one pair of memory cells are adjacent to each other, the one pair of memory cells being located between the memory cells of another pair of memory cells.

10. The folded bitline memory array of claim 1, wherein each of said pairs of memory cells in the substantially linear row are interleaved with each other.

11. The folded bitline memory array of claim 1, wherein the memory cells include DRAM cells.

12. The folded bitline memory array of claim 11, wherein each DRAM cell includes a planar capacitor.

13. The folded bitline memory array of claim 11, wherein each DRAM cell includes a metal-insulator-metal capacitor.

14. The folded bitline memory array of claim 1, wherein the memory cells include EPROM cells.

15. The folded bitline memory array of claim 1, wherein the memory cells include EEPROM cells.

16. The folded bitline memory array of claim 1, wherein the memory cells include Flash EEPROM cells.

17. The folded bitline memory array of claim 1, wherein the memory cells include ROM cells.

18. The folded bitline memory array of claim 1, wherein the memory cells include SRAM cells.

19. The folded bitline memory array of claim 1, wherein the memory cells of two adjacent rows of memory cells share the same bitline contacts.

20. The folded bitline memory array of claim 11, wherein the rows of DRAM memory cells with back-to-back capacitors are offset with each other by a predetermined pitch.

21. The folded bitline memory array of claim 20, wherein the predetermined pitch is up to one half of a memory cell pitch.

22. The folded bitline memory array of claim 1, wherein each wordline segment of the substantially linear row of pairs of memory cells are each coupled to 2 memory cells.

23. The folded bitline memory array of claim 1, wherein each conducting wordline is coupled to half of the memory cells of the row of memory cells.

24. The folded bitline memory array of claim 1, wherein alternate wordline segments of the substantially linear row of memory cells are connected to the same conducting wordline.

25. The folded bitline memory array of claim 1, wherein each wordline segment is coupled to 4 memory cells of the substantially linear row of memory cells.

26. The folded bitline memory array of claim 1, wherein the memory cells include dual port DRAM cells.

27. A folded bitline memory array comprising:

a first memory cell in a same linear row as a second memory cell;

a folded bitline connected to the first memory cell;

a complementary folded bitline connected to the second memory cell;

a first wordline segment coupled to the first memory cell; and

,

a second wordline segment coupled to the second memory cell, the first and second wordline segments being logically different wordlines.

28. The folded bitline memory array of claim 27, wherein the first memory cell shares a bitline contact with a third memory cell in the same linear row as a fourth memory cell, and the second memory cell shares a common bitline contact with the fourth memory cell.

29. The folded bitline memory array of claim 28, wherein the first, second, third and fourth memory cells include DRAM memory cells having planar storage capacitors.

30. The folded bitline memory array of claim 28, wherein the first, second, third and fourth memory cells include DRAM memory cells having metal-insulator-metal storage capacitors.

31. The folded bitline memory array of claim 28, wherein two rows of linearly adjacent memory cells are offset with each other by a predetermined pitch.