Combination of SRAM and MROM cells

• US 6,826,073 B2
• Filed: 06/30/2003
• Issued: 11/30/2004
• Est. Priority Date: 07/02/2002
• Status: Expired due to Fees

• Current Assignee: Brilliance Semiconductor Incorporated
• Original Assignee: Brilliance Semiconductor Incorporated
• Inventors: Liaw, Shion-Hau, Chen, Li-Yeh
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US10/608,527
• Publication Number:
  US 20040004882A1
• Time in Patent Office: 519 Days
• Field of Search: 365/154, 365/156, 365/104, 365/94
• US Class Current: 365/154
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells

Abstract

A new memory cell combination is disclosed. It includes a static random access memory (SRAM) unit and a mask read only memory (MROM) unit. The prior art separates the two memory units in different areas on a chip so that the circuit layout is not optimized. The disclosed cell combines them in the same area, saving more than 20% of the area.

Claims

1. A combination of static random access memory (SRAM) and mask read only memory (MROM) cells, including a SRAM unit and a ROM unit, wherein the static random access unit as a random access memory unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

the first transistor, the second transistor, the third transistor, and the fourth transistor forming an inverter;

the first transistor being complementary to the third transistor, the second transistor being complementary to the fourth transistor, which is characterized in that;

the ROM unit being a MROM is used to permanently store data and has a seventh transistor, with the feature that the ROM unit is embedded inside the SRAM unit, the ROM unit is in a cross region formed by an intersection of a polysilicon area and a source Vss of the fifth transistor and the sixth transistor with a ROM bit line contact next to the ROM unit.

2. The memory cell combination of claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are metal oxide semiconductor field effect transistors (MOSFET'"'"'s).

3. The memory cell combination of claim 1, wherein the SRAM unit and the ROM unit share the same word line.

4. The memory cell combination of claim 1, wherein the SRAM unit and the ROM unit share the same source (Vss) contact.

5. The memory cell combination of claim 1, wherein the SRAM unit and the ROM unit share the same X-decoder circuit.

6. A combination of static random access memory (SRAN) and mask read only memory (MROM) cells, including a SRAM unit and a ROM unit, wherein the static random access unit as a random access memory unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

the first transistor, the second transistor, the third transistor, and the fourth transistor forming an inverter;

the first transistor being complementary to the third transistor, the second transistor being complementary to the fourth transistor, which is characterized in that;

the ROM unit being a MROM is used to permanently store data and has a seventh transistor, with the feature that the ROM unit is formed in a cross region formed at an intersection of an active area extension where a polysilicon area and a source contact of the fifth transistor and the sixth transistor are located, so that the ROM unit is embedded inside the SRAM unit.

7. The memory cell combination of claim 6, wherein the ROM bit line contact next to the ROM unit.

8. The memory cell combination of claim 6, wherein the SRAM unit and the ROM unit share the same word line.

9. The memory cell combination of claim 6, wherein the SRAM unit and the ROM unit share the same source (Vss) contact.

10. The memory cell combination of claim 6, wherein the SRAM unit and the ROM unit share the same X-decoder circuit.

11. A combination of static random access memory (SRAN) and mask read only memory (MROM) cells, comprising:

a static random access unit, which has at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

wherein the first transistor, the second transistor, the third transistor, and the fourth transistor form an inverter, the first transistor is complementary to the third transistor, and the second transistor is complementary to the fourth transistor;

a read only memory (ROM) unit, which has at least a seventh transistor;

a first bit line, which is connected to the source/drain of the fifth transistor;

a second anti-bit line, which is connected to the source/drain of the sixth transistor;

a third bit line, which is connected to the source/drain of the seventh transistor; and

a word line, which is connected to the gates of the fifth transistor, the sixth transistor and the seventh transistor for controlling the fifth transistor, the sixth transistor and the seventh transistor.

12. The memory cell combination of claim 11, wherein the ROM unit is formed in a cross region formed at an intersection of an active area extension where a polysilicon area and a source contact of the fifth transistor and the sixth transistor are located, so that the ROM unit is embedded inside the SRAM unit.

13. The memory cell combination of claim 11, wherein the ROM unit is a mask read only memory (MROM).

14. The memory cell combination of claim 11, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are metal oxide semiconductor field effect transistors (MOSFET'"'"'s).

15. The memory cell combination of claim 11, wherein the ROM bit line contact next to the ROM unit.

16. The memory cell combination of claim 11, wherein the SRAM unit and the ROM unit share the same word line.

17. The memory cell combination of claim 11, wherein the SRAM unit and the ROM unit share the same source (Vss) contact.

18. The memory cell combination of claim 11, wherein the SRAM unit and the ROM unit share the same X-decoder circuit.