Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

• US 6,826,657 B1
• Filed: 09/10/2001
• Issued: 11/30/2004
• Est. Priority Date: 09/10/2001
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A.
• Primary Examiner(s): Elmore, Stephen
• Application Number:
  US09/948,769
• Time in Patent Office: 1,177 Days
• Field of Search: 711/104-105, 711/149, 711/152, 711/163, 711/170, 711/172, 711/173, 365/189.01, 365/189.02, 365/230.01, 365/230.02, 365/230.03, 365/230.04, 365/230.05
• US Class Current: 711/149
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory system comprising a memory module and a memory controller. The memory module comprises a memory component having a memory core for storing data therein, a first set of interface connections for providing access to the memory core, and a second set of interface connections for providing access to the memory core. The memory module also comprises access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections. The memory controller provides memory access signals to the memory module for selecting between the first mode and the second mode.

Claims

1. A memory system comprising:

a memory module comprising;

a memory component having a memory core for storing data therein;

a first set of interface connections for providing access to the memory core;

a second set of interface connections for providing access to the memory core; and

access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections; and

a memory controller for providing memory access signals to the memory module for selecting between the first mode and the second mode.

2. The memory system as defined in claim 1, wherein the memory controller includes a first data port and a second data port for providing access to the memory module, wherein the first data port is connected to the first set of interface connections for providing access between the memory controller and the memory module, the memory system further comprising:

a continuity module connected to the second data port and the second set of interface connections for providing access between the memory controller and the memory module.

3. The memory system as defined in claim 1, wherein the memory module is a first memory module having a first memory component with a first memory core and first access circuitry, wherein the memory controller includes a first data port and a second data port, wherein the first data port is connected to the first set of interface connections for providing access between the memory controller and the first memory module, the memory system further comprising:

a second memory module comprising;

a second memory component having a second memory core for storing data therein;

a third set of interface connections for providing access to the second memory core;

a fourth set of interface connections for providing access to the second memory core; and

second access circuitry for selecting between a first mode wherein a first portion of the second memory core is accessible through the third set of interface connections and a second portion of the second memory core is accessible through the fourth set of interface connections, and a second mode wherein both the first portion and the second portion of the second memory core are accessible through the third set of interface connections;

wherein the second data port is connected to the third set of interface connections for providing access between the memory controller and the second memory module, and wherein the second set of interface connections is connected to the fourth set of interface connections for providing access between the first memory module and the second memory module.

4. The memory system as defined in claim 1, wherein the memory module is a first memory module having a first memory component with a first memory core and first access circuitry, wherein the memory controller includes a first data port, a second data port, and a third data port, wherein the first data port is connected to the first set of interface connections for providing access between the memory controller and the first memory module, the memory system further comprising:

a second memory module comprising;

a second memory component having a second memory core for storing data therein;

a third set of interface connections for providing access to the second memory core;

a fourth set of interface connections for providing access to the second memory core; and

second access circuitry for selecting between a first mode wherein a first portion of the second memory core is accessible through the third set of interface connections and a second portion of the second memory core is accessible through the fourth set of interface connections, and a second mode wherein both the first portion and the second portion of the second memory core are accessible through the third set of interface connections; and

a third memory module comprising;

a third memory component having a third memory core for storing data therein;

a fifth set of interface connections for providing access to the third memory core;

a sixth set of interface connections for providing access to the third memory core; and

third access circuitry for selecting between a first mode wherein a first portion of the third memory core is accessible through the fifth set of interface connections and a second portion of the third memory core is accessible through the sixth set of interface connections, and a second mode wherein both the first portion and the second portion of the third memory core are accessible through the fifth set of interface connections;

wherein the third data port is connected to the sixth set of interface connections for providing access between the memory controller and the third memory module, wherein the second set of interface connections is connected to the third set of interface connections for providing access between the first memory module and the second memory module, and wherein the fourth set of interface connections is connected to the fifth set of interface connections for providing access between the second memory module and the third memory module.

5. The memory system as defined in claim 1, wherein the memory module is a first memory module having a first memory component with a first memory core and first access circuitry, wherein the memory controller includes a first data port, a second data port, and a third data port, wherein the first data port is connected to the first set of interface connections for providing access between the memory controller and the first memory module, wherein the second data port is connected to the second set of interface connections for also providing access between the memory controller and the first memory module, the memory system further comprising:

a second memory module comprising;

a second memory component having a second memory core for storing data therein;

a third set of interface connections for providing access to the second memory core;

a fourth set of interface connections for providing access to the second memory core; and

second access circuitry for selecting between a first mode wherein a first portion of the second memory core is accessible through the third set of interface connections and a second portion of the second memory core is accessible through the fourth set of interface connections, and a second mode wherein both the first portion and the second portion of the second memory core are accessible through the third set of interface connections;

wherein the third data port is connected to the third set of interface connections for providing access between the memory controller and the second memory module.

6. A memory system comprising:

a memory module comprising;

at least one memory component for providing memory storage locations for storing data therein;

a first set of interface connections for providing access to at least some of the memory storage locations;

a second set of interface connections for providing access to at least some of the memory storage locations; and

access circuitry for selecting between a first mode wherein a first group of the memory storage locations is accessible through the first set of interface connections and a second group of memory storage locations is accessible through the second set of interface connections, and a second mode wherein both the first group and the second group of memory storage locations are accessible through the first set of interface connections; and

a memory controller for providing memory access signals to the memory module for selecting between the first mode and the second mode.

7. The memory system as defined in claim 6, wherein the memory controller includes a first data port and a second data port for providing access to the memory module, wherein the first data port is connected to the first set of interface connections for providing access between the memory controller and the memory module, the memory system further comprising:

a continuity module connected to the second data port and the second set of interface connections for providing access between the memory controller and the memory module.

8. The memory system as defined in claim 6, wherein the memory module is a first memory module having at least one first memory component for providing first memory storage locations and first access circuitry, wherein the memory controller includes a first data port and a second data port, wherein the first data port is connected to the first set of interface connections for providing access between the memory controller and the first memory module, the memory system further comprising:

a second memory module comprising;

at least one second memory component for providing second memory storage locations for storing data therein;

a third set of interface connections for providing access to at least some of the second memory storage locations;

a fourth set of interface connections for providing access to at least some of the second memory storage locations; and

second access circuitry for selecting between a first mode wherein a first group of the second memory storage locations is accessible through the third set of interface connections and a second group of the second memory storage locations is accessible through the fourth set of interface connections, and a second mode wherein both the first group and the second group of the second memory storage locations are accessible through the third set of interface connections;

wherein the second data port is connected to the third set of interface connections for providing access between the memory controller and the second memory module, and wherein the second set of interface connections is connected to the fourth set of interface connections for providing access between the first memory module and the second memory module.

9. The memory system as defined in claim 6, wherein the memory module is a first memory module having at least one first memory component for providing first memory storage locations and first access circuitry, wherein the memory controller includes a first data port, a second data port, and a third data port, wherein the first data port is connected to the first set of interface connections for providing access between the memory controller and the first memory module, the memory system further comprising:

a second memory module comprising;

at least one second memory component for providing second memory storage locations for storing data therein;

a third set of interface connections for providing access to at least some of the second memory storage locations;

a fourth set of interface connections for providing access to at least some of the second memory storage locations; and

second access circuitry for selecting between a first mode wherein a first group of the second memory storage locations is accessible through the third set of interface connections and a second group of the second memory storage locations is accessible through the fourth set of interface connections, and a second mode wherein both the first group and the second group of the second memory storage locations are accessible through the third set of interface connections; and

a third memory module comprising;

at least one third memory component for providing third memory storage locations for storing data therein;

a fifth set of interface connections for providing access to at least some of the third memory storage locations;

a sixth set of interface connections for providing access to at least some of the third memory storage locations; and

third access circuitry for selecting between a first mode wherein a first group of the third memory storage locations is accessible through the fifth set of interface connections and a second group of the third memory storage locations is accessible through the sixth set of interface connections, and a second mode wherein both the first group and the second group of the third memory storage locations are accessible through the fifth set of interface connections;

wherein the third data port is connected to the sixth set of interface connections for providing access between the memory controller and the third memory module, wherein the second set of interface connections is connected to the third set of interface connections for providing access between the first memory module and the second memory module, and wherein the fourth set of interface connections is connected to the fifth set of interface connections for providing access between the second memory module and the third memory module.

10. The memory system as defined in claim 6, wherein the memory module is a first memory module having at least one first memory component for providing first memory storage locations and first access circuitry, wherein the memory controller includes a first data port, a second data port, and a third data port, wherein the first data port is connected to the first set of interface connections for providing access between the memory controller and the first memory module, wherein the second data port is connected to the second set of interface connections for also providing access between the memory controller and the first memory module, the memory system further comprising:

a second memory module comprising;

at least one second memory component for providing second memory storage locations for storing data therein;

a third set of interface connections for providing access to at least some of the second memory storage locations;

a fourth set of interface connections for providing access to at least some of the second memory storage locations; and

second access circuitry for selecting between a first mode wherein a first group of the second memory storage locations is accessible through the third set of interface connections and a second group of the second memory storage locations is accessible through the fourth set of interface connections, and a second mode wherein both the first group and the second group of the second memory storage locations are accessible through the third set of interface connections;

wherein the third data port is connected to the third set of interface connections for providing access between the memory controller and the second memory module.

11. A memory system comprising:

a memory controller/module connector having designated active and inactive address and data sites;

a memory controller having a plurality of groups of address and data lines, each group of address lines being connected to a respective active address site, each group of data lines being connected to a respective active data site; and

at least one memory module having a memory component with a memory core for storing data therein, each memory module having a plurality of sets of address and data contacts, each set of data contacts for providing access to the memory core;

wherein each memory module is mated with the memory controller/module connector such that at least one set of address contacts is connected to a respective active address site and at least one set of data contacts is connected to a respective active data site.

12. The memory system as defined in claim 11, wherein the memory controller includes multiplexing circuitry for steering individual address signals from the plurality of groups of address lines to particular active address sites.

13. The memory system as defined in claim 11, wherein the plurality of groups of data lines are divided so as to maximize bandwidth in the memory system.

14. A method for maximizing bandwidth in a memory system having a first memory module having a first memory capacity, the method comprising the steps of:

adding a second memory module having a second memory capacity to the memory system, wherein the second memory capacity is greater than the first memory capacity; and

removing the first memory module from the memory system, thereby preventing a memory capacity mismatch between the first and second memory modules and insuring maximum bandwidth in the memory system.

15. The method as defined in claim 14, further comprising the step of:

placing the first memory module in a memory module receptacle wherein the presence of the first memory module may be detected, but access to and from the first memory module is not permitted.