Profiling program execution into registers of a computer

• US 6,826,748 B1
• Filed: 06/24/1999
• Issued: 11/30/2004
• Est. Priority Date: 01/28/1999
• Status: Expired due to Term

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Ramesh, T. R., Thusoo, Shalesh, Saund, Gurjeet Singh, Patkar, Niteen Aravind, Hohensee, Paul H., Reese, David L., Yates, Jr., John S., Van Dyke, Korbin S.
• Primary Examiner(s): ZHEN, WEI Y
• Application Number:
  US09/339,749
• Time in Patent Office: 1,986 Days
• Field of Search: 717/127-135, 717/151-161, 714/37-57
• US Class Current: 717/130
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/45541 Bare-metal, i.e. hypervisor runs directly on hardware
• CPC Class Codes: G06F 9/45554 Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

A method and computer for performance of the method. While executing a program on a computer, the computer uses registers of a general register file for storage of instruction results. Profile information describing the profileable events is recorded into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.

Claims

1. A method, comprising:

while executing a program on a computer, the computer using registers of a general register file for storage of instruction results, detecting the occurrence of profileable events occurring in the instruction pipeline, and recording profile information describing the profileable events into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.

2. The method of claim 1, wherein at least one of the recorded instruction references indicates the address of the last byte of an instruction executed by the computer during the profiled execution interval.

3. The method of claim 1:

wherein the program has been compiled, without special consideration for execution profiling, into an instruction set in which an interpretation of an instruction depends on a processor mode not expressed in a binary representation of the instruction;

and further comprising recording profile information describing the processor mode during the profiled execution interval, the profile information being efficiently tailored to annotate the profiled binary code with sufficient processor mode information to resolve mode-dependency in the binary coding.

4. The method of claim 1 wherein:

the program has been compiled without special consideration for execution profiling; and

the program execution induces occurrence of events that match time-independent criteria of profileable events to be profiled;

and further comprising;

during a profile-quiescent interval of execution, recording no profile information in response to the occurrence of profileable events; and

commencing the profiled execution interval after a triggering event is detected, the triggering event being one of a predefined class of triggering events, the recorded profile information describing every event that matches the profileable event selection criteria induced after the triggering event, the recording continuing until a predetermined stop condition is reached.

5. The method of claim 4, the recorded profile information being efficiently tailored to identify all bytes of object code executed during the profiled execution interval, without reference to the binary code of the program.

6. The method of claim 4, wherein the triggering event is expiration of a timer.

7. The method of claim 4, wherein the triggering event is expiration of a timer, a frequency of the timer being configurable to control a resolution at which to monitor the instruction pipeline for profileable events.

8. The method of claim 1:

wherein the program has been compiled without special consideration for execution profiling;

and further comprising, without software intervention, recording for later analysis a profile entry noting the source and destination of a control flow event in which control flow of the program execution diverges from sequential execution.

9. The method of claim 1, the recorded profile information being efficiently tailored to identify all bytes of object code executed during the profiled execution interval, without reference to the binary code of the program.

10. The method of claim 1, further comprising:

recording profile information that records a sequence of events of the program, the sequence including every event during the profiled execution interval that matches time-independent criteria of profileable events to be profiled.

11. The method of claim 1, wherein at least a portion of the recording is performed by instructions speculatively introduced into the instruction pipeline.

12. The method of claim 1, wherein the recorded physical memory references include addresses of binary instructions referenced by an instruction pointer, and at least one of the recorded instruction references records the event of a sequential execution flow across a page boundary in the address space.

13. The method of claim 12, wherein at least one of the recorded instruction references records the event of a page boundary of the address space occurring within a single instruction.

14. The method of claim 12, wherein at least one of the recorded instruction references records the event of a page boundary between two instructions that are sequentially adjacent in the logical address space.

15. Computer hardware, comprising:

a general register file of registers;

an instruction pipeline comprising an arithmetic unit and configured to execute instructions fetched from a memory cache of the computer, the pipeline being in data communication with the registers for the general register file for storage of instruction results;

profile circuitry operatively interconnected with the instruction pipeline and configured to detect the occurrence of profileable events occurring in the instruction pipeline, and to capture information describing the profileable events into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.

16. The computer hardware of claim 15, wherein the profile data indicate the address of the last byte of an instruction executed by the computer during the profiled execution interval.

17. The computer of claim 15, wherein:

the first CPU is configured to execute instructions of an instruction set in which an interpretation of an instruction depends on a processor mode not expressed in a binary representation of the instruction; and

profile circuitry of the first CPU is configured to record profile information describing a processor mode during a profiled execution interval of the program, the profile information being efficiently tailored to annotate the profiled binary code with sufficient processor mode information to resolve mode-dependency in the binary coding.

18. The computer hardware of claim 15, further comprising:

profile control bits of the first CPU implemented;

in the computer hardware, values of the profile control bits controlling a resolution of the operation of profile circuitry of the first CPU;

a binary translator configured to translate programs coded in a first instruction set architecture into instructions of a second instruction set architecture;

a profile analyzer configured to analyze the recorded profile information, and to set the profile control bits to values to improve the operation of the binary translator.

19. The computer hardware of claim 15, wherein:

the profile circuitry is interconnected with the instruction pipeline to direct the recording by injection of an instruction into the pipeline, the instruction controlling the pipeline to cause the profileable event to be materialized in an architecturally-visible storage register of the computer.

20. The computer hardware of claim 19, wherein the instruction pipeline and profile circuitry are operatively interconnected to effect injection of multiple instructions into the instruction pipeline by the profile circuitry on the occurrence of a single profileable event.

21. The computer hardware of claim 15, wherein:

the profile circuitry comprises a plurality of storage registers arranged in a plurality of pipeline stages, information recorded in a given pipeline stage being subject to modification as a corresponding machine instruction progresses through the instruction pipeline.

22. The computer of claim 15, wherein:

during a profile-quiescent interval of execution of a program that has been compiled without special consideration for execution profiling and that induces events that match time-independent criteria of profileable events to be profiled, the profile circuitry is configured to record no profile information in response to the occurrence of profileable events; and

after a triggering event is detected, the triggering event being one of a predefined class of triggering events, the profile circuitry is configured to commence the profiled execution interval and to record profile information describing every event that matches the profileable event selection criteria induced during the profiled execution interval, the recording continuing until a predetermined stop condition is reached.

23. The computer of claim 22, wherein the triggering event is expiration of a timer.

24. The computer of claim 22:

wherein the criteria for profileable events divide the profileable events into initiating events and non-initiating events;

the profile circuitry being further designed;

after the triggering event is detected, to ignore non-initiating events; and

when an initiating event is detected, to commence recording the profile entries in the memory, describing every initiating and non-initiating event matching the profileable criteria during an interval following the triggering event.

25. The computer of claim 15, wherein the instruction pipeline and profile circuitry are further configured to effect recording of timestamp describing a time of the recorded events.

26. The computer of claim 15, wherein:

the instruction pipeline is configured to execute instructions of two substantially disjoint instruction sets, a native instruction set providing access to substantially all of the resources of the computer, and a non-native instruction set providing access to a subset of the resources of the computer.

27. A method, comprising:

while executing a program on a computer, the computer using registers of a general register file for storage of instruction operands, detecting the occurrence of profileable events occurring in the instruction pipeline, and recording profile information describing the profileable events into the general register file as the profileable events occur, without first capturing the information into a main memory of the computer.