Semiconductor device and method of manufacturing the same

• US 6,828,203 B2
• Filed: 10/17/2001
• Issued: 12/07/2004
• Est. Priority Date: 01/23/1998
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Inaba, Satoshi
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US09/977,933
• Publication Number:
  US 20020024107A1
• Time in Patent Office: 1,147 Days
• Field of Search: 438/301, 438/305, 438/306, 438/307, 438/299, 438/589, 438/585, 438/270, 438/592
• US Class Current: 438/305
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

There is provided a MISFET which suppresses a short-channel effect in a deep submicron region and has a low parasitic resistance, a low parasitic capacitance, and a small drain junction leakage current. A shallow concave is formed in a channel forming portion and an extension region forming portion of a MISFET, shallow ion implantation for forming an extension region is performed to a bottom surface of the shallow concave. Deep ion implantation for forming a source/drain region is performed to a silicon substrate adjacent to the concave, and the position of a peak concentration of the shallow ion implantation is caused to coincide with the position of a peak concentration of the deep ion implantation, so that a MISFET which suppresses a short-channel effect and has a low source/drain parasitic resistance, a low source/drain parasitic capacitance, and a small drain junction leakage current generated by SALICIDE steps can be provided. The MISFET according to the invention is preferably used as a means for providing a semiconductor substrate constituted by a high-speed CMOS circuit having a high integration level at a high yield and high reliability.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming an etching mask constituted by a first insulating film having an opening portion including a gate forming portion and source/drain extension regions forming portion on a surface of a semiconductor substrate;

forming a trench in the semiconductor substrate in correspondence with the opening portion of the etching mask;

forming a gate insulating film constituted by a second insulating film on an inner surface of the trench;

forming a gate material film on the second insulating film;

patterning the gate material film to form a gate on a central portion between both sides of the trench on a source/drain side through the second insulating film, while providing an exposed bottom surface of the trench between the central portion and both sides of the trench, on which the gate material film does not exist;

implanting impurity ions into at least the exposed bottom surface of the trench by using the entire gate as a mask to form source/drain extension regions;

forming a third insulating film to cover the surface of the semiconductor substrate;

forming gate sidewall spacers constituted by the third insulating film by using anisotropic etching to cover the inner surface of the trench extending on the source/drain side of the gate; and

implanting impurity ions into the source/drain regions by using the gate having the gate sidewall spacers as a mask to form a MIS-type field effect transistor having source/drain regions being close to or adjacent to side surfaces of the trench of the semiconductor substrate and connected to the source/drain extension regions on the bottom surface of the trench in which a position where an impurity concentration of the source/drain regions in the direction of depth is maximum substantially coincides with a position where an impurity concentration of the source/drain extension regions in the direction of depth is maximum.

2. A method of manufacturing a semiconductor device according to claim 1, wherein the trench is formed by isotropic etching such that the side surfaces of the trench on the source/drain side constitute a rounded surface.

3. A method of manufacturing a semiconductor device according to claim 1, wherein ion implantation for threshold voltage control of the MIS-type field effect transistor is performed to only the bottom surface of the trench.

4. A method of manufacturing a semiconductor device according to claim 1, wherein the first, second, and third insulating films are an SiO₂ film formed by an LPCVD method using TEAS, an SiO₂ film formed by thermal oxidation of silicon, and an SiN film formed by a CVD method, respectively.

5. A method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is formed to be stacked on a thermal oxidation film formed as a buffer layer on the semiconductor substrate.

6. A method of manufacturing a semiconductor device according to claim 1, further comprising after a silicide film of high melting point metal is formed on a silicon surface exposed to the source/drain regions and upper surfaces of the gate consisting of polysilicon by forming a high melting point metal film to cover the surface of the semiconductor substrate and performing heat treatment, removing the high melting point metal film remaining on the gate sidewall spacers.

7. A method of manufacturing a semiconductor device comprising:

forming an etching mask constituted by a first insulating film having an opening portion including a gate forming portion and source/drain extension regions forming portion on a surface of a semiconductor substrate;

forming a trench in the semiconductor substrate in correspondence with the opening portion of the etching mask;

forming a gate insulating film constituted by a second insulating film on an inner surface of the trench;

forming a gate material film on the second insulating film;

patterning the gate material film to form a gate on a central portion between both sides of the trench on a source/drain side through the second insulating film;

implanting impurity ions into at least a bottom surface of the trench by using the gate as a mask to form source/drain extension regions;

forming a third insulating film to cover the surface of the semiconductor substrate;

forming a gate sidewall spacers constituted by the third insulating film by using anisotropic etching to cover the inner surface of the trench extending on the source/drain side of the gate; and

implanting impurity ions into the source/drain regions by using the gate having the gate sidewall spacers as a mask to form a MIS-type field effect transistor having source/drain regions being close to or adjacent to side surfaces of the trench of the semiconductor substrate and connected to the source/drain extension regions on the bottom surface of the trench, in which a position where an impurity concentration of the source/drain regions in the direction of depth is maximum substantially coincides with a position where an impurity concentration of the source/drain extension regions in the direction of depth is maximum,

wherein an allowable misfit range required to make the maximum positions coincide with each other is about ±

0.01 μ

m with respect to the conditions for perfect coincidence.