Field-effect-controlled semiconductor component and method of fabricating a doping layer in a vertically configured semiconductor component

• US 6,828,605 B2
• Filed: 12/11/2001
• Issued: 12/07/2004
• Est. Priority Date: 12/11/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hansch, Walter, Fink, Christoph, Werner, Wolfgang, Eisele, Ignaz
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Lewis, Monica
• Application Number:
  US10/013,997
• Publication Number:
  US 20020125532A1
• Time in Patent Office: 1,092 Days
• Field of Search: 257/392, 257/403, 257/404, 257/213, 257/288, 257/342, 257/487, 257/20, 257/24, 257/101, 257/192, 257/548, 257/341, 257/333
• US Class Current: 257/213
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/365 Planar doping, e.g. atomic-plane doping, delta-doping
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A field-effect-controllable semiconductor component has at least one source zone and at least one drain zone of a first conductivity type, and at least one body zone of a second conductivity type. The body zone is provided between the source zone and the drain zone. In each case at least a first and a second region of the second conductivity type are provided in a channel zone. The first region has a first doping concentration and the second region has a second doping concentration, which is lower than the first doping concentration. The combination of the two regions produces a semiconductor component threshold voltage greater than zero and the on resistance is lower than that merely due to a channel zone doped with the first or second doping concentration.

Claims

1. A field-effect-controllable semiconductor configuration, comprising:

a semiconductor body;

a source zone and a drain zone of a first conductivity type disposed in said semiconductor body;

a body zone of a second conductivity type disposed between said source zone and said drain zone;

a gate electrode having a surface being adjacent said body zone and being configured to form a channel zone in said body zone if a gate potential is applied to said gate electrode, said channel zone having a current flow in a direction substantially parallel to said surface of said gate electrode upon application of the gate potential;

a dielectric insulating said gate electrode from said semiconductor body;

at least a first region and a second region of the second conductivity type provided in said channel zone, said first region extending adjacent said surface of said gate electrode into a depth of said semiconductor body and being disposed substantially perpendicular to the direction of current flow in said channel zone;

said first region having a first doping concentration, said second region having a second doping concentration, said second doping concentration being lower than said first doping concentration;

said source zone, said drain zone, said body zone, and said gate electrode forming a semiconductor component having a threshold voltage and a given on resistance; and

said first region and said second region being configured such that a combination of said first region and said second region results in the threshold voltage being greater than zero and in the given on resistance being lower than an on resistance resulting from a channel zone being doped with only one of said first doping concentration and said second doping concentration.

2. The semiconductor configuration according to claim 1, wherein said first region has a given thickness, said channel zone has a channel length, said given thickness is smaller than said channel length.

3. The semiconductor configuration according claim 1, wherein said first region is configured as a delta doping layer.

4. The semiconductor configuration according to claim 3, wherein said delta doping layer has a layer thickness in a range from a few atomic layers up to 20 nm.

5. The semiconductor configuration according to claim 3, wherein said delta doping layer has a doping density per unit area of greater than 10¹¹ cm ⁻

2.

6. The semiconductor configuration according to claim 3, wherein said delta doping layer has a doping concentration dimensioned such that a total quantity of doping atoms in said channel zone at least ensures a blocking capability of said semiconductor component, if said semiconductor component is in an off state.

7. The semiconductor configuration according to claim 1, wherein said second region has an intrinsic doping concentration which is lower than said first doping concentration by at least a factor of 100.

8. The semiconductor configuration according to claim 1, wherein said second doping concentration is lower than said first doping concentration by at least a factor of 100.

9. The semiconductor configuration according to claim 1, wherein said first region is provided within said channel zone and is spaced apart from said source zone via at least said second region.

10. The semiconductor configuration according to claim 1, including a further second region, said first region being provided within said channel zone and being spaced apart from said source zone via one of said second region and said further second region.

11. The semiconductor configuration according to claim 1, wherein said first region has a surface and is oriented within said channel zone such that, with a voltage applied between said drain zone and said source zone and with a gate potential applied to said gate electrode, a direction of current flow is substantially perpendicular to said surface of said first region.

12. The semiconductor configuration according to claim 1, wherein said semiconductor component is configured as a MOSFET.

13. The semiconductor configuration according to claim 1, wherein said semiconductor component is configured as a normally off MOSFET.

14. The semiconductor configuration according to claim 12, wherein said MOSFET is configured as a vertical transistor.

15. The semiconductor configuration according to claim 12, wherein said MOSFET is configured as a component selected from the group consisting of a D-MOSFET, a U-MOSFET, and a V-MOSFET.

16. The semiconductor configuration according to claim 12, wherein said MOSFET is configured as a mesa component.

17. The semiconductor configuration according to claim 12, wherein said MOSFET is formed with a trench, said gate electrode insulated via said dielectric is provided in said trench.

18. The semiconductor configuration according to claim 1, including a drift zone of the first conductivity type, said drift zone being provided between said body zone and said drain zone and being connected to said drain zone.

19. The semiconductor configuration according to claim 1, including:

further semiconductor components having respective channel zones and respective first regions and second regions of the second conductivity type provided in said channel zones; and

said semiconductor component and said further semiconductor components forming a cell array, said cell array having a center region and an edge region, said first regions having thicknesses varying between said center region and said edge region.

20. The semiconductor configuration according to claim 1, including:

further semiconductor components having respective channel zones and respective first regions and second regions of the second conductivity type provided in said channel zones; and

said semiconductor component and said further semiconductor components forming a cell array, said cell array having a center region and an edge region, said first regions having thicknesses decreasing from said center region to said edge region.

21. The semiconductor configuration according to claim 1, wherein said semiconductor component is configured as a smart power transistor.