Semiconductor device having a die pad supported by a die pad supporter

• US 6,828,659 B2
• Filed: 05/30/2001
• Issued: 12/07/2004
• Est. Priority Date: 05/31/2000
• Status: Expired due to Term

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Iwakiri, Toshihiko
• Primary Examiner(s): Zarneke, David A.
• Assistant Examiner(s): SARKAR, ASOK K
• Application Number:
  US09/866,920
• Publication Number:
  US 20020027270A1
• Time in Patent Office: 1,287 Days
• Field of Search: 257/666, 257/667, 257/669, 257/670, 257/674, 257/676
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/29007 Layer connector smaller than the underlying bonding area
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32055 being circular or elliptic
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49544 Deformation absorbing parts in the lead frame plane, e.g. meanderline shape H01L23/49562 takes precedence
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor package includes a semiconductor chip which is mounted on a die pad which is smaller than the semiconductor chip, a die pad supporter which supports the die pad, the die pad supporter having a stress absorbing portion, the stress absorbing portion is disposed under the semiconductor chip.

Claims

1. A semiconductor device comprising:

a die pad;

a die pad supporter which supports the die pad;

a plurality of inner leads arranged to surround the die pad; and

a semiconductor chip which has a size larger in area than that of said die pad and which is mounted on said die pad;

wherein said die pad supporter includes a frame portion which ha a rectangular shape, a first portion connected between a side portion of said frame portion and the die pad, and a second portion which extends from a corner portion of said frame portion to between a pair of said inner leads, and wherein the frame portion and he first portion are disposed between the inner leads and the die pad.

2. A semiconductor device according to claim 1, comprising a plurality of said second portions, wherein each of said second portions is disposed between said inner leads and disposed substantially parallel with said inner leads adjacent to the second portions.

3. A semiconductor device according to claim 2, wherein said second portions extend to four different directions.

4. A semiconductor device according to claim 1, wherein said semiconductor chip has a first surface on which an integrated circuit is formed and a second surface which is opposite said first surface, and wherein said frame portion is arranged adjacent the second surface of the semiconductor chip.

5. A semiconductor device according to claim 1, wherein said second portion of said die pad supporter has a down-set portion which is located at an area between the pair of said inner leads.

6. A semiconductor device comprising:

a die pad;

a plurality of inner leads arranged to surround the die pad;

a semiconductor chip which has a size larger in area than that of said die pad and which is mounted on said die pad;

a frame portion which substantially surrounds the die pad and is disposed between said inner leads and said die pad;

first die pad supporters each of which supports the frame portion from four directions; and

a second die pad supporter which connects the frame portion and said die pad;

wherein said second die pad supporter is extended along a direction different from directions in which the first die pad supporters are extended.

7. A semiconductor device according to claim 6, wherein said semiconductor chip is disposed on the frame portion.

8. A semiconductor device according to claim 7, wherein said first die pad supporters and said second die pad supporter are staggered at the frame portion.

9. A semiconductor device according to claim 6, wherein said frame portion has substantially rectangular shape, and wherein said first die pad supporters each support substantially coiner portions of said frame portion, and wherein said second die pad supporter connects at a side portion of said frame portion.

10. A semiconductor device according to claim 6, wherein said first die pad supporters have a down-set portion which is located at an area between respective pairs of said inner leads.