Low inductance power distribution system for an integrated circuit chip

• US 6,828,666 B1
• Filed: 06/18/1998
• Issued: 12/07/2004
• Est. Priority Date: 03/21/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Herrell, Dennis J., Dolbear, Thomas P.
• Primary Examiner(s): Cao, Phat X.
• Application Number:
  US09/099,758
• Time in Patent Office: 2,364 Days
• Field of Search: 257/691, 257/697, 257/698, 257/686, 257/723
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19106 in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 2201/10545 Related components mounted on both sides of the PCB
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array

Abstract

A low impedance electrical pathway from decoupling capacitance located on a circuit board to an integrated circuit chip. The integrated circuit includes multiple power and ground C4 bumps and is positioned on a first side of an integrated circuit carrier which is positioned on a first side of a circuit board. The integrated circuit carrier includes lateral conductors such as voltage and ground power planes. Power and ground carrier vias extend from the voltage and ground power planes, respectively, to the first side of the carrier, and power and ground subgroups of carrier vias extend from the voltage and ground power planes, respectively, to power and ground solder balls on a second side of the carrier. The circuit board includes power and ground plated through holes extending from contact pads on the first side of the circuit board to contact pads on a second side of the circuit board. Decoupling capacitors are positioned on the second side of the circuit board. The decoupling capacitors have positive and negative electrodes are electrically coupled to the power and ground plated through holes respectively. The C4 power and ground bumps, the power and ground carrier vias, the power and ground carrier via subgroups, the power and ground solder balls, the contact pads, the power and ground plated through holes, and the positive and negative electrodes are arranged in anti-parallel tessellations to reduce the inductance of a loop circuit from the decoupling capacitors to the integrated chip circuit.

Claims

1. An apparatus comprising:

an integrated circuit carrier including;

first and second groups of carrier vias extending substantially from a first side of said carrier towards a second side of said carrier;

a circuit board including;

first and second groups of circuit board vias extending substantially from a first side of said circuit board towards a second side of said circuit board;

a loop circuit having a loop inductance, said loop circuit defined from said first group of circuit board vias, through said first group of carrier vias to said first side of said circuit board and back through said second group of carrier vias, through said second group of circuit board vias;

wherein said carrier vias of said first and second groups are arranged in an anti-parallel tessellation and include a substantial majority of all carrier vias for coupling respective power supply voltages; and

wherein said circuit board vias of said first and second groups are arranged in an anti-parallel tessellation and include a substantial majority of all circuit board vias for coupling respective power supply voltages.

2. An apparatus as recited in claim 1 wherein:

said carrier further includes;

a first group of at least one lateral conductor;

a second group of at least one lateral conductor;

third and fourth groups of carrier vias extending from said first and second groups of at least one lateral conductor, respectively, substantially to a second side of said carrier;

wherein said loop circuit is further defined from said first group of circuit board vias, through said third group of carrier vias, through said first group of at least one lateral conductor, through said first group of carrier vias, said loop circuit is further defined through said second group of carrier vias, through said second group of at least one lateral conductor, through said fourth group of carrier vias, through said second group of circuit board vias.

3. An apparatus as recited in claim 2 wherein said third group of carrier vias are subgrouped to define a first group of carrier via subgroups and said fourth group of carrier vias are subgrouped to define a second group of carrier via subgroups, said first group of carrier via subgroups electrically couple said first group of at least one lateral conductor to said first group of circuit board vias and second group of carrier via subgroups electrically couple said second group of at least one lateral conductor to said second group of circuit board vias, wherein said first and second groups of carrier via subgroups are arranged in an anti-parallel tessellation.

4. An apparatus of claim 2 wherein:

said first group of at least one lateral conductor includes a first power plane;

said first group and said third group of carrier vias are electrically connected to said first power plane;

said second group of at least one lateral conductor includes a second power plane;

said second group and said fourth group of carrier vias are electrically connected to said second power plane.

5. An apparatus of claim 2 wherein an average length of a carrier via of said first and second groups of carrier vias is greater than an average length of a carrier via of said third and fourth groups of carrier vias.

6. An apparatus as recited in claim 1 further comprising:

first and second groups of electrically conducting structures on said first side of said circuit board;

third and fourth groups of electrically conductive structures on said second side of said circuit board;

said loop circuit further defined from said third group of electrically conductive structures, through said first group of circuit board vias, through said first group of electrically conductive structures, through said first group of carrier vias, said loop circuit further defined through said second group of carrier vias, through said second group of electrically conductive structures, through said second group of circuit board vias, to said fourth group of electrically conductive structures;

wherein said electrically conductive structures of said first and second groups are arranged in an anti-parallel tessellation.

wherein said electrically conductive structures of said third and fourth groups are arranged in an anti-parallel tessellation.

7. An apparatus as recited in claim 1 wherein a portion of said loop inductance associated with said first and second groups of carrier vias is less than 0.001 of an average inductance for an individual carrier via of said first and second groups.

8. An apparatus as recited in claim 1 wherein:

said anti-parallel tessellation of said first and second groups of carrier vias defines a checkerboard pattern of carrier vias of said first and said second groups.

9. An apparatus as recited in claim 1 wherein:

said anti-parallel tessellation of said first and second groups of carrier vias defines alternating rows of carrier vias of said first and said second groups.

10. An apparatus as recited in claim 1 wherein:

said anti-parallel tessellation of said first and second groups of carrier vias defines anti-parallel pairs of carrier vias, each pair including a carrier via from said first group and from said second group;

each anti-parallel pair has a mutual coupling of at least 0.80 of an average inductance of said carrier via from said first group and from said second group of said each pair.

11. An apparatus as recited in claim 1 wherein:

said anti-parallel tessellation of said first and second groups of circuit board vias defines a checkerboard pattern of circuit board vias of said first and second groups.

12. An apparatus as recited in claim 1 wherein:

said anti-parallel tessellation of said first and second groups of circuit board vias defines alternating rows of circuit board vias of said first and second groups.

13. An apparatus as recited in claim 1 wherein said portion of said loop inductance associated with said first and second groups of circuit board vias is less than 0.04 of an average inductance for an individual circuit board via of said first and second groups.

14. An apparatus as recited in claim 1 further comprising:

a decoupling capacitor located on said second side of said circuit board, said decoupling capacitor having a first electrode electrically coupled to a circuit board via of said first group of circuit board vias, said decoupling capacitor having a second electrode electrically coupled to a circuit board via of said second group of circuit board vias.

15. An apparatus as recited in claim 14 wherein said decoupling capacitor has a third electrode electrically coupled to a circuit board via of said first group of circuit board vias, said decoupling capacitor has a fourth electrode electrically coupled to a circuit board via of said second group of circuit board vias.

16. An apparatus as recited in claim 1 further comprising:

an integrated circuit chip located said first side of said carrier, said integrated circuit chip including a first group of conductive structures electrically coupled to said first group of carrier vias, said integrated circuit chip including a second group of electrically conductive structures electrical coupled to said second group of carrier vias.

17. An apparatus comprising:

an integrated circuit carrier including first and second groups of carrier vias extending substantially from a first side of said carrier towards a second side of said carrier;

a circuit board including first and second groups of circuit board vias extending substantially from a first side of said circuit board towards a second side of said circuit board; and

a loop circuit having a loop inductance, said loop circuit defined from said first group of circuit board vias, through said first group of carrier vias to said first side of said circuit board and back through said second group of carrier vias, through said second group of circuit board vias;

wherein said carrier vias of said first and second groups and said circuit board vias of said first and second groups are both arranged in respective anti-parallel tessellations, each such anti-parallel tessellation including an arrangement of multiple, parallely oriented conductive structures of the loop circuit wherein current flow through a first group of the conductive structures is in an opposing direction to the current flow through a second group of the conductive structures and wherein the arrangement provides for a reduction in the inductance of the loop circuit due to the mutual coupling among the conductive structures of the two groups and due to the multiple parallel conductive structures of each group.

18. The apparatus of claim 17,

wherein said carrier vias of said first and second groups together from a substantial majority of all carrier vias for coupling to respective first and second power supply voltages.

19. The apparatus of claim 17,

wherein said circuit board vias of said first and second groups together from a substantial majority of all circuit board vias for coupling to respective first and second power supply voltages.