Heterogeneous interconnection architecture for programmable logic devices

• US 6,828,824 B2
• Filed: 05/30/2003
• Issued: 12/07/2004
• Est. Priority Date: 10/12/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Altera Toronto Co.
• Inventors: Rose, Jonathan, Betz, Vaughn
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US10/449,753
• Publication Number:
  US 20040017222A1
• Time in Patent Office: 557 Days
• Field of Search: 326/38-41, 326/101, 326/47, 257/499, 257/503, 333/12
• US Class Current: 326/47
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.

Claims

1. A programmable logic device comprising:

a plurality of function blocks;

a first plurality of a programmable interconnect resource for programmably interconnecting at least some of said function blocks; and

a second plurality of said programmable interconnect resource for programmably interconnecting some of said function blocks, said second plurality comprising about 20% of all said programmable interconnect resource on said programmable logic device.

2. The programmable logic device of claim 1 wherein said function blocks comprise logic blocks.

3. The programmable logic device of claim 1 wherein said function blocks comprise input/output circuits.

4. The programmable logic device of claim 1 wherein said first plurality of said programmable interconnect resource comprises a first group of signal wires spaced apart from each other by a first wire-to-wire spacing.

5. The programmable logic device of claim 4 wherein said second plurality of said programmable interconnect resource comprises a second group of signal wires spaced apart from each other by a second wire-to-wire spacing, said second wire-to-wire spacing greater than said first wire-to-wire spacing.

6. The programmable logic device of claim 1 wherein said first plurality of said programmable interconnect resource comprises a first type of buffer and said second plurality of said programmable interconnect resource comprises a second type of buffer, said second type of buffer having fewer stages of circuit logic than said first type of buffer.

7. The programmable logic device of claim 1 wherein said first plurality of said programmable interconnect resource comprises a balanced multiplexer and said second plurality of said programmable interconnect resource comprises an unbalanced multiplexer.

8. The programmable logic device of claim 1 wherein said second plurality of said programmable interconnect resource comprises pairs of signal wires, each said pair having a grounded signal wire between them.

9. A programmable logic device comprising:

a plurality of function blocks; and

a first group of signal wires spaced apart from each other by a first wire-to-wire spacing and connected to at least some of said function blocks; and

a second group of signal wires spaced apart from each other by a second wire-to-wire spacing and connected to some of said function blocks, said second group of signal wires comprising about 20% of all said signal wires on said programmable logic device.

10. A programmable logic device comprising:

a plurality of function blocks; and

a first group of signal wires each having a first width, said first group of signal wires connected to at least some of said function blocks; and

a second group of signal wires each having a second width wider than said first width, said second group of signal wires connected to some of said function blocks and comprising about 20% of all said signal wires on said programmable logic device.

11. A programmable logic device comprising:

a plurality of function blocks; and

a plurality of programmable interconnect resources for programmably interconnecting a first one of said function blocks to a second one of said function blocks, said resources comprising;

a first group of signal wires wherein at least one wire of said first group connects said first function block to said second function block in accordance with a first operational parameter comprising signal propagation speed; and

a second group of signal wires wherein at least one wire of said second group connects said first function block to said second function block in accordance with a second operational parameter comprising circuit area.

12. The programmable logic device of claim 11 wherein each wire of said first group of signal wires has a first width and each wire of said second group of signal wires has a second width different than said first width.

13. The programmable logic device of claim 11 wherein side-by-side wires of said first group of signal wires are spaced apart from each other by a first wire-to-wire spacing and side-by-side wires of said second group of signal wires are spaced apart from each other by a second wire-to-wire spacing different than said first wire-to-wire spacing.

14. A programmable logic device comprising:

a plurality of function blocks; and

a plurality of programmable interconnect resources for programmably interconnecting said function blocks, said resources comprising;

a first group of signal wires wherein said signal wires are spaced apart from each other by a first wire-to-wire spacing; and

a second group of signal wires wherein said signal wires of said second group are spaced apart from each other by a larger second wire-to-wire spacing;

wherein;

signal wires of said first group are connected to a first subplurality of said function blocks in accordance with a first operational parameter comprising circuit area; and

signal wires of said second group are connected to a second subplurality of said function blocks in accordance with a second operational parameter comprising reliability, said reliability including a degree of freedom from signal transition glitches caused by crosstalk.

15. The programmable logic device of claim 14 wherein some function blocks belong to both said first and second subpluralities of function blocks.

16. A programmable logic device comprising:

a plurality of function blocks; and

a plurality of programmable interconnect resources for programmably interconnecting said function blocks, said resources comprising a first group of signal wires and a second group of signal wires wherein a pair of said signal wires from said second group has a grounded signal wire running parallel between them to at least substantially electrically shield each said wire of said pair;

wherein;

signal wires of said first group are connected to a first subplurality of said function blocks in accordance with a first operational parameter selected from the group consisting of circuit area, propagation speed, and signal routing flexibility; and

signal wires of said second group are connected to a second subplurality of said function blocks in accordance with a second operational parameter comprising reliability.

17. The programmable logic device of claim 16 wherein said reliability comprises a degree of freedom from signal transition glitches caused by crosstalk.

18. The programmable logic device of claim 16 wherein some function blocks belong to both said first and second subpluralities of function blocks.