Clock receiver circuit for on-die salphasic clocking

• US 6,828,841 B2
• Filed: 08/29/2003
• Issued: 12/07/2004
• Est. Priority Date: 08/29/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Krishnamurthy, Ram K., Soumyanath, Krishnamurthy, Anders, Mark A.
• Primary Examiner(s): Le, Dinh T.
• Application Number:
  US10/652,668
• Publication Number:
  US 20040036520A1
• Time in Patent Office: 466 Days
• Field of Search: 327/333, 327/295, 327/291, 327/563, 327/561, 327/164, 327/562, 327/246, 327/293, 327/296, 327/297, 327/50, 327/52
• US Class Current: 327/291
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Claims

1. A microelectronic die comprising:

a differential clock distribution medium having first and second differential signal lines, said first differential signal line to carry a first differential signal component and said second differential signal line to carry a second differential signal component;

a first clock receiver circuit to generate a true clock signal, said first clock receiver circuit having a positive differential clock input and a negative differential clock input, said positive differential clock input coupled to said first differential signal line and said negative differential clock input coupled to said second differential signal line; and

a second clock receiver circuit to generate a complement clock signal, said second clock receiver circuit having a positive differential clock input and a negative differential clock input, said positive differential clock input coupled to said second differential signal line and said negative differential clock input coupled to said first differential signal line.

2. The microelectronic die of claim 1 wherein:

said first and second clock receiver circuits have substantially the same circuit architecture.

3. The microelectronic die of claim 1 wherein:

said first clock receiver circuit includes a folded cascode differential amplifier.

4. The microelectronic die of claim 2 wherein:

said second clock receiver circuit includes a folded cascode differential amplifier.

5. The microelectronic die of claim 1 wherein:

said first and second differential signal components are sinusoidal and said true and complement clock signals are square waves.

6. The microelectronic die of claim 2 wherein:

said differential clock distribution medium is part of a salphasic clock distribution network.

7. The microelectronic die of claim 1 wherein:

said microelectronic die is part of a microprocessor unit.