SRAM power-up system and method
First Claim
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1. An SRAM cell array, comprising:
- an array of SRAM cells arranged in rows and columns, the array including a wordline for each row of the array and a pair of complementary digit lines for each column of the array, each of the SRAM cells having an a pair of access transistors coupled to respective complementary digit lines for a respective column and a gate coupled to a wordline for a respective row; and
a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access transistors non-conductive in a power-up mode.
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Abstract
A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.
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Citations
10 Claims
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1. An SRAM cell array, comprising:
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an array of SRAM cells arranged in rows and columns, the array including a wordline for each row of the array and a pair of complementary digit lines for each column of the array, each of the SRAM cells having an a pair of access transistors coupled to respective complementary digit lines for a respective column and a gate coupled to a wordline for a respective row; and
a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access transistors non-conductive in a power-up mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
a respective bias transistor coupled between a supply node and each of the digit lines;
a bias supply transistor coupled between a supply voltage and the supply node of each bias transistor; and
a power-up circuit coupled to a gate of the bias supply transistor, the power-up circuit being operable in a normal mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor conductive, and being operable in the power-up mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor non-conductive.
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3. The SRAM cell array of claim 2 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, wherein the bias supply transistor comprises a PMOS transistor coupled to a positive supply voltage, wherein each of the bias transistors comprise a PMOS transistor, and wherein the power-up circuit is operable to couple substantially ground potential to the gate of the PMOS bias supply transistor in the normal mode and to couple the gate of the PMOS bias supply transistor to substantially the positive supply voltage in the power-up mode.
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4. The SRAM cell array of claim 1 wherein the bias circuit comprises:
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a respective bias transistor coupled between a supply terminal and each of the digit lines; and
a power-up circuit coupled to the supply terminal of each of the bias transistors, the power-up circuit being operable in a normal mode to couple a supply voltage to the supply terminal of each of the bias transistors, and being operable in the power-up mode isolate the power supply voltage from the supply terminal of each of the bias transistors.
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5. The SRAM cell array of claim 4 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.
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6. The SRAM cell array of claim 1 wherein the bias circuit comprises:
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a respective bias transistor coupled between a supply voltage and each of the digit lines; and
a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit receiving a power-up signals and a digit line load signal corresponding to the bias transistors for each pair of complimentary digit lines, the power-up circuit being operable in response to a power-up signal indicative of a normal mode to couple each of the digit line load signals to the gate of the respective bias transistor to renders the bias transistors conductive, and being operable in response to a power-up signal indicative of a power-up mode to couple a voltage to the gate of the bias transistors that renders the bias transistors non-conductive.
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7. The SRAM cell array of claim 6 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.
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8. The SRAM cell array of claim 1 wherein the bias circuit comprises:
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a respective bias transistor coupled between a supply voltage and each of the digit lines; and
a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit being operable in a normal mode to apply a voltage to a gate of each of the bias transistors that renders the bias transistors conductive, and being operable in a power-up mode to apply a voltage to the gate of each of the bias transistors that renders the bias transistors non-conductive.
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9. The SRAM cell array of claim 8 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.
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10. The SRAM cell array of claim 1 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein the bias circuit is operable to couple a positive current to the digit lines in the normal mode and to terminate coupling the positive current from the digit lines in the power-up mode.
Specification