Programming of nonvolatile memory cells

• US 6,829,172 B2
• Filed: 05/28/2002
• Issued: 12/07/2004
• Est. Priority Date: 05/04/2000
• Status: Expired due to Term

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Finzi, David, Maayan, Eduardo, Bloom, Ilan, Eitan, Boaz, Cohen, Zeev
• Primary Examiner(s): HO, HOAI V
• Application Number:
  US10/155,217
• Publication Number:
  US 20030072192A1
• Time in Patent Office: 924 Days
• Field of Search: 365/185.22, 365/185.28, 365/185.19, 365/185.01
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming

Abstract

A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

Claims

1. A method for programming a multi-level NROM cell having more than one programmed state to a target programmed state, the method comprising:

applying a drain, a source and a gate voltage to said cell;

verifying a threshold voltage level of said cell; and

if verified threshold voltage level is below a threshold voltage level associated with said target programmed state;

increasing said drain voltage; and

maintaining said gate voltage at a constant level during at least a part of said step of increasing, and

repeating said steps of applying, verifying, increasing and maintaining until said cell'"'"'s threshold voltage level is substantially equal to the threshold voltage level associated with said target programmed state.

3. The method according to claim 1 or 2, wherein said step of increasing includes the step of stepping said drain voltage.

4. The method according to claim 3, wherein said step of stepping includes the step of executing non-linear steps.

5. The method according to claim 3, wherein said step of stepping includes the step of executing equal amplitude steps.

6. The method according to claim 5, wherein each equal amplitude step produces an equivalent step in a threshold voltage of said multi-level NROM cell.

7. The method according to claim 3, wherein said step of stepping includes the step of executing steps of equal time duration.

8. The method according to claim 3, wherein said step of stepping includes the step of executing steps of unequal time duration.

9. The method according to claim 1 or 2 and further comprising the step of dialing in an initial drain voltage.

10. The method according to claim 1 or 2, wherein said step of maintaining includes the step of changing said gate voltage at least once.

11. The method according to claim 1 or 2, wherein said step of maintaining includes the step of maintaining said gate voltage constant throughout said step of increasing.

12. The method according to claim 1 or 2, wherein said step of applying includes the step of applying a maximum gate voltage to said gate.

13. The method according to claim 1 or 2, wherein said step of applying includes the step of beginning said drain voltage at a low voltage level.

14. The method according to claim 1 or 2, wherein said step of applying includes the step of stopping said drain voltage at a voltage level slightly above a saturated threshold voltage level of said cell.

15. The method according to claim 1 or 2, wherein said step of repeating occurs 3-7 times.

2. A method for controlling the programming time of a multi-level NROM cell having more than one programmed state to a target programmed state, the method comprising:

applying a drain, a source and a gate voltage to said cell;

verifying a threshold voltage level of said cell; and

if verified threshold voltage level is below a threshold voltage level associated with said target programmed state;

increasing said drain voltage; and

maintaining said gate voltage at a constant level during at least a part of said step of increasing, and

repeating said steps of applying, verifying, increasing and maintaining until said cell'"'"'s threshold voltage level is substantially equal to the threshold voltage level associated with said target programmed state.

16. A method for confining charge within a predefined region of a retention layer of a multi-level NROM cell having more than one programmed state and having a gate, the method comprising, during programming to a target programmed state one storage area of said cell;

applying an incrementally increasing drain voltage to a diffusion area acting as a drain of said cell;

maintaining a constant gate voltage on said gate during at least a part of said step of applying;

verifying a threshold voltage level of said cell; and

if verified threshold voltage level is below a threshold voltage level associated with said target programmed state, repeating said steps of applying, maintaining and verifying until said cell substantially reaches the threshold voltage level associated with said target programmed state.

20. The method according to any one of claims 16-19, wherein said step of applying begins at a low voltage level.

21. The method according to any one of claims 16-19, wherein said step of repeating includes the step of stopping at a voltage level slightly above a saturated threshold voltage level of said cell.

22. The method according to any one of claims 16-19 and further comprising the step of applying a maximum gate voltage to said gate of said cell.

23. The method according to any one of claims 16-19, wherein said predefined region is close to said diffusion area.

25. The method according to any one of claims 16-19, wherein said step of applying include the step of stepping said drain voltage.

26. The method according to claim 25, wherein said step of stepping includes the step of executing non-linear steps.

27. The method according to claim 25, wherein said step of stepping includes the step of executing equal amplitude steps.

28. The method according to claim 27, wherein each equal amplitude step produces an equivalent step in a threshold voltage of said multi-level NROM cell.

29. The method according to claim 25, wherein said step of stepping includes the step of executing steps of equal time duration.

30. The method according to claim 25, wherein said step of stepping includes the step of executing steps of unequal time duration.

31. The method according to any one of claims 16-19 and further comprising the step of dialing in an initial drain voltage.

32. The method according to any one of claims 16-19, wherein said step of maintaining includes the step of changing said gate voltage at least once.

33. The method according to any one of claims 16-19, wherein said step of maintaining includes the step of maintaining said gate voltage constant throughout said step of applying.

17. A method for retaining charge in a multi-level NROM cell having more than one programmed state and having a gate and a retention layer, the method comprising:

confining said charge within a predefined region of said retention layer of said cell by;

applying an incrementally increasing drain voltage to a diffusion area acting as a drain of said cell;

maintaining a constant gate voltage on said gate during at least a part of said step of applying;

verifying a threshold voltage level of said cell; and

if verified threshold voltage level is below a threshold voltage level associated with a target programmed state, repeating said steps of confining and verifying until said cell'"'"'s threshold voltage level substantially reaches the threshold voltage level associated with said target programmed state.

18. A method for retaining charge in a multi-level NROM cell having more than one programmed state and having a gate and a retention layer, the method comprising:

providing a compact spatial charge distribution within a predefined region of said retention layer of said cell by;

applying an incrementally increasing drain voltage to a diffusion area acting as a drain of said cell;

maintaining a constant gate voltage on said gate during at least a part of said step of applying;

verifying a threshold voltage level of said cell; and

if verified threshold voltage level is below a threshold voltage level associated with a target programmed state, repeating said steps of providing and verifying until said cell'"'"'s threshold voltage level substantially reaches the threshold voltage level associated with said target programmed state.

34. A multi-level NROM cell having charge retained by the method of claim 18 or 19.

35. A charge distribution as created by the method of claim 18 or 19.

19. A method for retaining the separation distance between two charge regions in a multi-level NROM cell having more than one programmed state and having a gate and two diffusion areas, the method comprising, for each charge region:

applying an incrementally increasing drain voltage to the diffusion area closest to said charge region;

maintaining a constant gate voltage on said gate during at least a part of said step of applying;

verifying a threshold voltage level of said cell; and

if verified threshold voltage level is below a threshold voltage level associated with a target programmed state, repeating said steps of applying, maintaining and verifying until said cell'"'"'s threshold voltage level substantially reaches the threshold voltage level associated with said target programmed state.

24. The method according to claim 19, wherein said charge regions are close to one of said two diffusion areas.

36. A method for programming a multi-level NROM cell having more than one programmed state to a target programmed state, the method comprising, during programming:

applying a drain, a source and a gate voltage; and

while keeping said gate voltage at at least one constant level, increasing said drain voltage until said cell substantially reaches saturation.

37. A method for controlling a change in the threshold voltage of a multi-level NROM cell having more than one programmed state, wherein the cell receives a drain, a source and a gate voltage, the method comprising, during programming to a target programmed state, varying said drain voltage while keeping said gate voltage at at least one constant level.

38. A method for controlling the programming time of a multi-level NROM cell having more than one programmed state to a target programmed state, the method comprising:

applying a drain, a source and a gate voltage; and

while keeping said gate voltage at at least one constant level, incrementally increasing said drain voltage during programming, until said cell reaches saturation.

39. A method for programming an array of multi-level NROM cells having more than one programmed state and having varying programming speeds, the array having bit lines and word lines, the method comprising:

providing a gate voltage to one of said word lines;

providing a source voltage to a first bit line and a drain voltage to a second bit line; and

varying said drain voltage while keeping said gate voltage at a constant level until said array of cells reach saturation.

40. A method for retaining the separation distance between two charge regions in a multi-level NROM cell, the multi-level NROM cell having more than one programmed state and having a gate and two diffusion areas, the method comprising, while applying at least one constant gate voltage to said gate, for each charge region, applying an incrementally increasing bit line voltage to the diffusion area closest to said charge region, until said cell reaches saturation.

41. A method for retaining charge in a multi-level NROM cell having more than one programmed state and having a gate and a retention layer, the method comprising providing a compact spatial charge distribution within a predefined region of said retention layer of said cell by applying an incrementally increasing bit line voltage to a diffusion area acting as a drain of said cell, while applying at least one constant gate voltage to said gate, until said cell reaches saturation.