Semiconductor memory, method of testing semiconductor memory, and method of manufacturing semiconductor memory

• US 6,829,181 B1
• Filed: 04/24/2003
• Issued: 12/07/2004
• Est. Priority Date: 11/02/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Seitoh, Akira
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US10/399,975
• Time in Patent Office: 593 Days
• Field of Search: 365/189.1, 365/189.07, 365/201, 365/230.01, 365/230.03, 365/236, 714/718, 714/719, 714/720
• US Class Current: 365/201
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/0405 comprising complete test loop
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 29/38 Response verification devices

Abstract

Testing circuits each including a comparator for comparing data read from semiconductor memories to be tested with expected value data and thereby detecting coincidences/non-coincidences, and a counter for counting the number of non-coincidences detected are provided on a printed board for burn-in or within semiconductor memories to be tested. The semiconductor memories can be tested by the testing circuits respectively.

Claims

1. A semiconductor memory comprising:

a memory circuit; and

a testing circuit including a comparator for comparing data read from the memory circuit with expected value data to thereby detect coincidences/non-coincidences therebetween and a counter for counting the number of the detected non-coincidences, said memory circuit, said testing circuit, and a result-of-determination storage circuit storing a result of failure determination based on a result of comparison by the comparator being formed over the same semiconductor chip,

wherein the memory circuit is tested by the testing circuit while addresses are being updated, the number of addresses at which failures are detected, is configured so as to be counted by the counter, and information obtained by ORing a previous result of failure determination read from the result-of-determination storage circuit with a result of failure/non-failure determination based on the result of comparison by the comparator is configured so as to be stored in the result-of-determination storage circuit.

2. The semiconductor memory according to claim 1, wherein the result of counting by the counter is configured so as to be capable of being outputted to the outside.

3. The semiconductor memory according to claim 1, wherein each of word lines for the result-of-determination storage circuit is selected by a select signal of an address decoder for selecting each word line in a memory array of the memory circuit, and the result of failure determination based on the result of comparison by the comparator is configured so as to be stored in the result-of-determination storage circuit in association with each memory row of the memory circuit to be tested.

4. The semiconductor memory according to claim 1, wherein the result-of-determination storage circuit is provided at part of the memory circuit to be tested.

5. The semiconductor memory according to claim 1, wherein the counter is configured so as to count the failure information read from the result-of-determination storage circuit.

6. The semiconductor memory according to claim 1, wherein the counter is configured so as to count the failure information read from the result-of-determination storage circuit and output an overflow signal when the counter counts subsequently-inputted determining failure information and counts the same up to a predetermined number.

7. The semiconductor memory according to claim 1, wherein the memory circuit to be tested comprises nonvolatile memory elements, and the result-of-determination storage circuit is constituted of volatile memory elements.