Memory device

• US 6,829,187 B2
• Filed: 05/20/2002
• Issued: 12/07/2004
• Est. Priority Date: 11/19/1999
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Paul, Steffen, Seifert, Martin
• Primary Examiner(s): Tran, M.
• Application Number:
  US10/151,090
• Publication Number:
  US 20020196682A1
• Time in Patent Office: 932 Days
• Field of Search: 365/189.07, 365/205
• US Class Current: 365/205
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

A memory device has a read amplifier with either a variable input resistance and/or the input connections that may be linked to one or both poles of a voltage source using one or more transistors. Additionally, or alternatively the read amplifier is also applied in the decoder devices for choosing the memory cell to he read out or to be written to.

Claims

1. A memory device, comprising:

a plurality of memory cells for storing data; and

a read amplifier for determining the data of a relevant one of said plurality of said memory cells by evaluating a characteristic of a current flowing between said relevant one of said plurality of said memory cells and said read amplifier;

said characteristic being selected from the group consisting of a magnitude of said current and a direction of said current; and

said read amplifier having a variable input impedance.

2. The memory device according to claim 1, wherein:

said read amplifier has components with dimensions; and

said input impedance of said read amplifier can be varied by varying said dimensions of selected ones of said components of said read amplifier.

3. The memory device according to claim 1, wherein:

said read amplifier has components;

said read amplifier has a drive for selected ones of said components; and

said input impedance of said read amplifier can be varied by varying said drive.

4. The memory device according to claim 1, wherein:

said read amplifier includes an input and a symmetrically constructed amplifier stage having two identically configured amplifier branches connected to said input.

5. The memory device according to claim 4, wherein:

each one of said amplifier branches has a transistor operated in a common-gate configuration and a load resistor following said transistor.

6. The memory device according to claim 4, wherein:

each one of said amplifier branches includes an input and a transistor connecting said input to ground.

7. The memory device according to claim 4, comprising:

further amplifier branches constructed complementary to each other;

each one of said further amplifier branches connected in parallel with a respective one of said amplifier branches at said input.

8. The memory device according to claim 1, wherein:

said read amplifier includes an input and an asymmetrically constructed amplifier stage having two complementary configured amplifier branches connected to said input.

9. The memory device according to claim 8, wherein:

each one of said amplifier branches has a transistor operated in a common-gate configuration and a load resistor following said transistor.

10. The memory device according to claim 8, wherein:

each one of said amplifier branches includes an input and a transistor connecting said input to ground.

11. The memory device according to claim 8, comprising:

further amplifier branches constructed complementary to each other;

each one of said further amplifier branches connected in parallel with a respective one of said amplifier branches at said input.

12. The memory device according to claim 1, wherein:

said read amplifier includes an input and an asymmetrically constructed amplifier stage having only one amplifier branch connected to said input.

13. The memory device according to claim 12, wherein:

said amplifier branch has a transistor operated in a common-gate configuration and a load resistor following said transistor.

14. The memory device according to claim 12, wherein:

said amplifier branch includes an input and a transistor connecting said input to ground.

15. The memory device according to claim 12, comprising:

a further amplifier branch constructed complementary to said amplifier branch;

said further amplifier branch connected in parallel with said amplifier branch at said input.

16. The memory device according to claim 1, wherein:

said read amplifier includes an input and an amplifier stage having two amplifier branches connected to said input;

each one of said amplifier branches has a transistor operated in a common gate configuration and a load resistor following said transistor.

17. The memory device according to claim 16, wherein:

said transistor in each one of said amplifier branches has a gate terminal receiving a voltage acting to vary said input impedance of said read amplifier.

18. The memory device according to claim 17, wherein:

said read amplifier has adjustable components; and

said voltage applied to said gate terminal of said transistor in each one of said amplifier branches can be varied by adjusting said adjustable components.

19. The memory device according to claim 17, wherein:

said read amplifier has components; and

said voltage applied to said gate terminal of said transistor in each one of said amplifier branches can be varied by appropriately dimensioning said components.

20. The memory device according to claim 16, comprising:

coupling branches;

each one of said coupling branches providing a voltage from one of said amplifier branches;

said transistor in each one of said amplifier branches having a gate terminal receiving said voltage from a respective one of said coupling branches.

21. The memory device according to claim 16, comprising:

a voltage divider providing voltages;

coupling branches;

said transistor in each one of said amplifier branches having a gate terminal; and

said coupling branches applying a respective one of said voltages from said voltage divider to said gate terminal of said transistor in each one of said amplifier branches.

22. The memory device according to claim 21, wherein:

said load resistor is formed by a CMOS voltage divider.

23. The memory device according to claim 21, wherein:

said voltage divider is formed by a CMOS voltage divider.

24. The memory device according to claim 16, wherein:

said load resistor is constructed to provide various voltages.

25. The memory device according to claim 16, wherein:

said load resistor is formed by a resistor that can be tapped at a plurality of points.

26. The memory device according to claim 16, wherein:

said load resistor is formed by a diode-connected transistor and a transistor that forms a load resistor; and

said transistor that forms said load resistor is connected in series with said diode-connected transistor.

27. The memory device according to claim 16, comprising:

coupling branches for controlling said transistor in each one of said amplifier branches;

each one of said coupling branches including a voltage amplifier selected from the group consisting of an inverting amplifier and a non-inverting amplifier.

28. The memory device according to claim 27, wherein:

said voltage amplifier is formed by a load resistor followed by a transistor operated in a common-gate configuration.

29. The memory device according to claim 27, wherein:

said voltage amplifier is formed by a load resistor followed by a transistor operated in a common-source connection.

30. The memory device according to claim 16, wherein:

said resistor is formed by a transistor.

31. The memory device according to claim 1, comprising:

voltage dividers; and

coupling branches;

said read amplifier including an input and an amplifier stage having two amplifier branches connected to said input;

said voltage dividers located between said amplifier branches, said voltage dividers having inversely acting taps; and

each one of said amplifier branches having a transistor with a gate terminal receiving a voltage from one of said taps of said voltage dividers.

32. The memory device according to claim 1, wherein:

said read amplifier includes an amplifier stage that has two amplifier branches;

each one of said amplifier branches includes an input and a transistor that connects said input to ground; and

said transistor has a gate terminal that receives a voltage from one of said amplifier branches.

33. A memory device, comprising:

a plurality of memory cells for storing data;

a read amplifier for determining the data of a relevant one of said plurality of said memory cells by evaluating a characteristic of a current flowing between said relevant one of said plurality of said memory cells and said read amplifier, said characteristic being selected from the group consisting of a magnitude of said current and a direction of said current;

a line through which said current flows; and

at least one transistor for connecting said line to at least one terminal of a voltage source.

34. A memory device, comprising:

a plurality of memory cells for storing data; and

a decoding device having at least two mutually cooperating decoding units for selecting ones of said plurality of said memory cells;

at least a first one of said decoding units including a read amplifier; and

said read amplifier for performing an operation selected from the group consisting of receiving, evaluating, and forwarding information selected from the group consisting of data from at least a second one of said decoding units and signals from at least said second one of said decoding units.