Adaptive equalizer having a variable step size influenced by output from a trellis decoder
First Claim
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1. An adaptive equalizer comprising:
- a decision device;
an FIR filter coupled to the decision device;
a DFE coupled to the decision device, the DFE producing a DFE output;
a Viterbi decoder coupled to the decision device, the Viterbi decoder producing a reliability output and a decoded output;
a mapper coupled to receive the decoded output of the Viterbi decoder and to generate a mapped and scaled output;
wherein the error signal is generated by delaying the DFE output by a number of cycles equal to a number of cycles the Viterbi decoder uses to generate the reliability output and subtracting the delayed decoded output of the DFE from the mapped and sealed output of the mapper;
wherein a magnitude of change in the coefficient of the adaptive equalizer is selected based at least in part upon the reliability output and at least in part upon the error signal.
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Abstract
An adaptive equalizer comprises a decision device; a decision feedback equalizer coupled to the decision device; an FIR filter coupled to the decision device; and a trellis decoder coupled to the decision device, adapted to provide a reliability output and a decoded output. An error signal is generated by subtracting an output of the decision feedback equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.
97 Citations
1 Claim
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1. An adaptive equalizer comprising:
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a decision device;
an FIR filter coupled to the decision device;
a DFE coupled to the decision device, the DFE producing a DFE output;
a Viterbi decoder coupled to the decision device, the Viterbi decoder producing a reliability output and a decoded output;
a mapper coupled to receive the decoded output of the Viterbi decoder and to generate a mapped and scaled output;
wherein the error signal is generated by delaying the DFE output by a number of cycles equal to a number of cycles the Viterbi decoder uses to generate the reliability output and subtracting the delayed decoded output of the DFE from the mapped and sealed output of the mapper;
wherein a magnitude of change in the coefficient of the adaptive equalizer is selected based at least in part upon the reliability output and at least in part upon the error signal.
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Specification
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Current AssigneeTrident Microsystems Limited (Avnet Incorporated)
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Original AssigneeMicronas Semiconductors Incorporated
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InventorsCitta, Richard W., Xia, Jingsong, LoPresto, Scott M., Zhang, Wenjun, Song, Hangbin
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Primary Examiner(s)Bocure, Tesfaldet
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Assistant Examiner(s)Tran, Khanh Cong
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Application NumberUS09/875,720Publication NumberTime in Patent Office1,280 DaysField of Search375/229, 375/232, 375/233, 375/236, 375/262, 375/263, 375/264, 375/265, 375/284, 375/285, 375/340, 375/341, 375/346, 375/348, 375/349, 375/350, 375/343, 348/607, 348/622, 348/608, 348/614, 714/774, 714/780, 714/786, 714/792, 714/794, 714/795, 704/242, 708/300, 708/322, 708/323US Class Current375/232CPC Class CodesH04L 1/0054 Maximum-likelihood or seque...H04L 1/006 Trellis-coded modulationH04L 1/1671 the supervisory signal bein...H04L 2025/0349 as a feedback filterH04L 2025/03617 Time recursive algorithms H...H04L 2025/03624 Zero-forcingH04L 2025/03687 of step sizeH04L 25/03057 with a recursive structure ...
