Method and apparatus for selectively compacting test responses
First Claim
1. An apparatus used in testing of an integrated circuit, comprising:
- a circuit under test that is part of the integrated circuit;
at least one spatial compactor to compress test responses from the circuit under test; and
a selector circuit coupled to the circuit under test and coupled to the spatial compactor and wherein the selector circuit controls the masking of one or more of the test responses that are received from the circuit under test.
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Accused Products
Abstract
A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
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Citations
23 Claims
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1. An apparatus used in testing of an integrated circuit, comprising:
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a circuit under test that is part of the integrated circuit;
at least one spatial compactor to compress test responses from the circuit under test; and
a selector circuit coupled to the circuit under test and coupled to the spatial compactor and wherein the selector circuit controls the masking of one or more of the test responses that are received from the circuit under test. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An apparatus used in testing of an integrated circuit, comprising:
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a circuit under test that is part of the integrated circuit;
at least one spatial compactor to compress test responses from the circuit under test; and
a selector circuit coupled to the circuit under test and coupled to the spatial compactor and wherein the selector circuit controls the masking of one or more of the test responses that are received from the circuit under test; and
wherein the selector circuit includes a register that stores a flag that when activated allows all the test responses pass to the compactor and that when deactivated allows none of the test responses pass to the compactor.
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13. A method for selectively compacting test responses of a circuit under test, comprising:
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receiving N test responses from scan chains in the circuit under test;
selectively preventing between 0 and N of the test responses from being passed to a spatial compactor while allowing the remaining test responses to be passed to the spatial compactor; and
spatially compacting the test responses passed to the spatial compactor. - View Dependent Claims (14, 15, 16, 17, 18)
loading the scan chains with predetermined test patterns for testing the circuit under test; and
generating and storing test responses in response to applying the test patterns to the circuit under test.
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16. The method of claim 13, wherein selectively preventing includes controlling which test responses are passed to the spatial compactor by using external automatic testing equipment.
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17. The method of claim 13, further including:
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loading the scan chains with predetermined test patterns;
storing test responses in the scan chains;
identifying one scan chain as a scan chain of interest and passing only the test response within the identified scan chain to the compactor while preventing all other test responses from being passed to the compactor.
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18. The method of claim 13, wherein selectively preventing the test responses from being passed to the spatial compactor includes preventing one or more bits of a test response from being passed to the compactor while allowing other bits of the test response to pass to the compactor.
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19. An apparatus used in testing of integrated circuits, comprising:
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scan chains within the integrated circuit;
a selector circuit coupled to the scan chains; and
a spatial compactor coupled to the selector circuit. - View Dependent Claims (20, 21)
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22. An apparatus used in testing of integrated circuits, comprising:
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scan chains within the integrated circuit, a selector circuit coupled to the scan chains; and
a spatial compactor coupled to the selector circuit; and
wherein the spatial compactor includes a feedback-free network of linear gates.
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23. A method for selectively compacting test responses of a circuit under test, comprising:
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receiving test responses from at least one scan chain in the circuit under test;
selectively masking bits from the said at least one scan chain on a per-clock cycle basis while allowing the remaining bits of the scan chain to be passed to a spatial compactor; and
spatially compacting the test responses passed to the spatial compactor.
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Specification