Method and apparatus for generating multi-layer routes

• US 6,829,757 B1
• Filed: 02/12/2002
• Issued: 12/07/2004
• Est. Priority Date: 06/03/2001
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Caldwell, Andrew, Teig, Steven
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US10/076,121
• Time in Patent Office: 1,029 Days
• Field of Search: 438/737, 716/1, 716/5, 716/12, 716/13, 716/2, 716/11, 370/256
• US Class Current: 716/112
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Some embodiments of the invention provide a method of generating a multi-layer topological path for a layout that has multiple layers. This method specifies a set of path expansions from a first topological item to a second topological item on a first layer of the layout. For a potential via expansion from the second topological item to a third topological item on a second layer of the layout, the method (1) identifies a first region on the first layer for the second topological item, (2) identifies a second region on the second layer the third topological item, (3) determines whether an intersection of the first and second regions is sufficiently large to contain a via, and (4) if the intersection is sufficiently large, adds the potential via expansion to the specified set of path expansions.

Claims

1. For a layout that has multiple layers, a method of generating a multi-layer topological path comprising:

a) specifying a set of path expansions from a first topological item to a second topological item, wherein the second topological item is on a first layer of the layout; and

b) for a potential via expansion from the second topological item to a third topological item on a second layer of the layout,

identifying a first region on the first layer for the second topological item;

identifying a second region on the second layer for the third topological item;

determining whether an intersection of the first and second regions is larger than a threshold area; and

if the intersection is larger than the threshold area, adding the potential via expansion to the specified set of path expansions.

2. The method of claim 1, wherein if the intersection is not larger than the threshold area, discarding the potential via expansion.

3. The method of claim 1 further comprising:

before specifying the set of path expansions, decomposing the layout into a plurality of faces, wherein each face has a set of edges and an interior space between the edges;

wherein at least one of the second and third topological items represents an interior space of a face.

4. The method of claim 3, wherein the second topological item represents an interior space of a first face on the first layer, and the third topological item represents an interior space of a second face on the second layer.

5. The method of claim 3, wherein the layout is an IC layout.

6. The method of claim 5, wherein the IC layout includes a plurality of routable elements, wherein decomposing the layout comprises:

specifying a plurality of nodes along boundaries of the routable elements; and

defining edges between the nodes.

7. The method of claim 1, wherein each path expansion starts at a source topological item and ends with a destination topological item.

8. A computer program stored on a computer readable medium, wherein the computer program generates, for a layout that has multiple layers, a multi-layer topological path, the computer program comprising:

a) a first set of instructions for specifying a set of path expansions from a first topological item to a second topological item, wherein the second topological item is on a first layer of the layout;

b) for a potential via expansion from the second topological item to a third topological item on a second layer of the layout,

a second set of instructions for identifying a first region on the first layer for the second topological item;

a third set of instructions for identifying a second region on the second layer for the third topological item;

a fourth set of instructions for determining whether an intersection of the first and second regions is larger than a threshold area; and

a fifth set of instructions for adding the potential via expansion to the specified set of path expansions, when the intersection is larger than the threshold area.

9. The computer program of claim 8 further comprising a sixth set of instructions for identifying another potential expansion from the second topological item when the intersection is not larger than the threshold area.

10. The computer program of claim 8 further comprising:

a sixth set of instruction for decomposing, before specifying the set of path expansions, the layout into a plurality of faces, wherein each face has a set of edges and an interior space between the edges;

wherein at least one of the second and third topological items represents an interior space of a face.

11. The computer program of claim 10, wherein the second topological item represents an interior space of first face on the first layer, and the third topological item represents an interior space of a second face on the second layer.

12. The computer program of claim 10, wherein the layout is an IC layout.

13. The computer program of claim 12, wherein the IC layout includes a plurality of routable elements, wherein the sixth set of instructions comprises:

a seventh set of instructions for specifying a plurality of nodes along boundaries of the routable elements; and

an eight set of instructions for defining edges between the nodes.

14. The computer program of claim 13, wherein each path expansion starts at a source topological item and ends with a destination topological item.

15. For an integrated circuit layout that has multiple layers, a method of generating a multi-layer topological path comprising:

a) identifying a set of path expansions from a first topological item to a second topological item on a first layer of the layout;

b) identifying a first region on the first layer for the second topological item, and a second region on the second layer for a third topological item that is reachable from the second topological item through a via expansion;

c) determining whether an intersection of the first and second regions is larger than a threshold area; and

d) adding the potential via expansion to the specified set of path expansions when the intersection is larger than the threshold area.

16. The method of claim 15 further comprising discarding the potential via expansion when the intersection is not larger than the threshold area.

17. The method of claim 15 further comprising:

before specifying the set of path expansions, decomposing the layout into a plurality of faces, wherein each face has a set of edges and an interior space between the edges;

wherein at least one of the second and third topological items represents an interior space of a face.

18. The method of claim 17, wherein the second topological item represents an interior space of a first face on the first layer, and the third topological item represents an interior space of a second face on the second layer.

19. The method of claim 17, wherein the IC layout includes a plurality of routable elements, wherein decomposing the layout comprises:

specifying a plurality of nodes along boundaries of the routable elements; and

defining edges between the nodes.

20. A computer program stored on a computer readable medium, wherein the computer program generates, for an integrated circuit layout that has multiple layers, a multi-layer topological path, the computer program comprising sets of instructions for:

a) identifying a set of path expansions from a first topological item to a second topological item on a first layer of the layout;

b) identifying a first region on the first layer for the second topological item, and a second region on the second layer for a third topological item that is reachable from the second topological item through a via expansion;

c) determining whether an intersection of the first and second regions is larger than a threshold area; and

d) adding the potential via expansion to the specified set of path expansions when the intersection is larger than the threshold area.

21. The computer program of claim 20 further comprising a set of instructions for discarding the potential via expansion when the intersection is not larger than the threshold area.

22. The computer program of claim 20 further comprising a set of instructions for decomposing the layout into a plurality of faces, before specifying the set of path expansions, wherein each face has a set of edges and an interior space between the edges;

wherein at least one of the second and third topological items represents an interior space of a face.

23. The computer program of claim 22, wherein the second topological item represents an interior space of a first face on the first layer, and the third topological item represents an interior space of a second face on the second layer.

24. The computer program of claim 22, wherein the IC layout includes a plurality of routable elements, wherein the set of instructions for decomposing the layout comprises a set of instructions for:

specifying a plurality of nodes along boundaries of the routable elements; and

defining edges between the nodes.