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Fully depleted silicon-on-insulator CMOS logic

  • US 6,830,963 B1
  • Filed: 10/09/2003
  • Issued: 12/14/2004
  • Est. Priority Date: 10/09/2003
  • Status: Active Grant
First Claim
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1. A method for generating a fully depleted body structure in a silicon-on-insulator device having a substrate, the method comprising:

  • providing an extractor contact coupled to the body structure in the silicon-on-insulator layer; and

    providing an extractor voltage such that the extractor contact is reverse biased and minority carriers in the body structure are removed.

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