Fully depleted silicon-on-insulator CMOS logic

• US 6,830,963 B1
• Filed: 10/09/2003
• Issued: 12/14/2004
• Est. Priority Date: 10/09/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/682,590
• Time in Patent Office: 432 Days
• Field of Search: 257/347, 257/392, 257/476, 257/548
• US Class Current: 438/149
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.

Claims

1. A method for generating a fully depleted body structure in a silicon-on-insulator device having a substrate, the method comprising:

providing an extractor contact coupled to the body structure in the silicon-on-insulator layer; and

providing an extractor voltage such that the extractor contact is reverse biased and minority carriers in the body structure are removed.

2. The method of claim 1 wherein the substrate is at ground potential.

3. The method of claim 1 wherein the extractor contact is coupled to a p-type silicon on the insulator.

4. The method of claim 1 wherein the extractor contact is coupled to an n-type silicon on the insulator.

5. The method of claim 1 wherein the silicon-on-insulator device has a drain region and the method further comprises applying a drain voltage to the drain region.

6. The method of claim 5 wherein the extractor voltage is greater than the drain voltage.

7. The method of claim 2 wherein the extractor voltage is less than the substrate potential.

8. A method for generating a fully depleted body structure in a PMOS silicon-on-insulator device having a substrate, a control gate, a drain region, and a source region, the method comprising:

applying an extractor voltage to an extractor contact coupled to the body structure in the silicon-on-insulator layer; and

applying a substrate voltage to the substrate such that the extractor voltage is greater than the substrate voltage.

9. The method of claim 8 wherein the substrate voltage is ground potential.

10. The method of claim 8 wherein the extractor contact is coupled to an n-type silicon on the substrate.

11. The method of claim 8 and further including applying a positive voltage to the control gate to erase a charge stored in the device.

12. A method for generating a fully depleted body structure in an NMOS silicon-on-insulator device having a substrate, a control gate, a drain region, and a source region, the method comprising:

applying an extractor voltage to an extractor contact coupled to the body structure in the silicon-on-insulator layer; and

applying a substrate voltage to the substrate such that the extractor voltage is less than the substrate voltage.

13. The method of claim 12 wherein the extractor contact is coupled to a p-type silicon on the substrate.

14. The method of claim 12 and further including applying a negative voltage to the control gate to erase a charge stored in the device.

15. A method for generating a fully depleted body region in an NROM flash memory device using a silicon-on-insulator structure, the device having a substrate, a control gate, a drain region, and a source region, the method comprising:

applying an extractor voltage to an extractor contact coupled to the body structure in the silicon-on-insulator layer; and

applying a substrate voltage to the substrate such that the extractor voltage is less than the substrate voltage.

16. The method of claim 15 wherein the extractor contact is comprised of a p-type silicon.