Method of fabricating flip chip semiconductor device utilizing polymer layer for reducing thermal expansion coefficient differential

• US 6,830,999 B2
• Filed: 06/17/2002
• Issued: 12/14/2004
• Est. Priority Date: 09/12/1997
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Deshmukh, Rajan D.
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US10/173,182
• Publication Number:
  US 20020197768A1
• Time in Patent Office: 911 Days
• Field of Search: 438/106, 438/108, 438/110, 438/112, 438/113, 438/118, 438/584, 438/597, 438/612, 438/613, 438/618, 438/622, 438/623, 438/624, 438/455, 438/458, 438/460, 228/101, 228/178, 228/179.1, 228/180.1, 228/180.21, 228/180.22, 298/54, 298/25, 298/29, 298/74, 298/76, 298/84
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An improved flip chip assembly is disclosed of the type where a semiconductor chip having a certain thermal expansion coefficient is directly mounted via solder bumps on the metallization pattern of a circuit substrate having a different thermal expansion coefficient. A base layer comprised of a polymer material is disposed over the surface of the chip, between the chip and the substrate, and the solder bumps are placed over the base layer; the base layer modifies the effective thermal expansion coefficient of the solder bumps to approximate that of the substrate, thus reducing the thermal expansion coefficient differential at the junction of the chip and the substrate.

Claims

1. A method of preparing a semiconductor chip for mounting to a circuit substrate having a first thermal expansion coefficient, the method comprising the steps of:

(a) providing a semiconductor chip having at least one bond pad disposed on its active side and a second thermal expansion coefficient different from the first thermal expansion coefficient;

(b) monolithically applying a polymer over the surface of the active side of the chip and the at least one bond pad to form a polymer layer;

(c) removing the polymer layer from the bond pad, the layer abutting the bond pad;

(d) depositing an interconnect metallic layer over a portion of the surface of the polymer layer for coupling the bond pad to the surface of the polymer layer; and

(e) disposing at least one solder bump on the polymer layer, the solder bump being in registration with the metallic layer for coupling the solder bump to the bond pad,

wherein the step of monolithically applying the polymer is controlled to provide the polymer layer with a particular thickness that causes the at least one solder bump to have an effective thermal expansion coefficient, as modified by the polymer layer, between the first thermal expansion coefficient and the second thermal expansion coefficient.

2. The method according to claim 1, in which the step of applying the metallic layer comprises (i) applying a removable polymeric mask over the surface of the chip to define a surface region for application of the interconnect metallic layer;

and (ii) removing the polymeric mask once the interconnect metallic layer has been applied.

3. A method for preparing a plurality of semiconductor chips for mounting to at least one circuit substrate having a first thermal expansion coefficient, the method comprising the steps of:

(a) providing a plurality of semiconductor chips on a wafer, each of the plurality of semiconductor chips having an active side on one side of the wafer, thereby defining a plurality of active sides, wherein at least one bond pad is disposed on each active side to define a plurality of bond pads;

(b) monolithically applying a polymer layer over the wafer so that the polymer layer is disposed over the plurality of active sides and plurality of bond pads;

(c) removing portions of the polymer layer to expose the plurality of bond pads, the layer abutting the plurality of bond pads; and

(d) depositing metal over the wafer so that an interconnect metallic layer couples a portion of the surface of the polymer layer to the plurality of bond pads; and

(e) disposing a plurality of solder bumps on the interconnect metallic layer,

wherein the at least one substrate has a first thermal expansion coefficient, and the plurality of semiconductor chips have a second thermal expansion coefficient different from the first thermal expansion coefficient, thereby defining a thermal expansion coefficient differential, and

wherein the step of monolithically applying the polymer is controlled to provide the polymer layer with a particular thickness that reduces the thermal expansion coefficient differential when the plurality of semiconductor chips are mounted to the at least one substrate.

4. The method of claim 3, further comprising a step of dicing the wafer to separate the plurality of semiconductor chips to provide individual semiconductor chips.

5. The method of claim 4 in which the step of dicing the wafer is performed before the step of disposing the plurality of solder bumps.

6. The method of claim 4 in which the step of dicing the wafer is performed after the step of disposing the plurality of solder bumps.

7. A method of preparing a semiconductor chip for mounting to a circuit substrate having a first thermal expansion coefficient, the method comprising the steps of:

(a) providing a semiconductor chip having at least one bond pad disposed on its active side and a second thermal expansion coefficient different from the first thermal expansion coefficient;

(b) monolithically applying a polymer over the surface of the active side of the chip and the at least one bond pad to form a polymer layer;

(c) removing the polymer layer from the bond pad, the layer abutting the bond pad;

(d) depositing an interconnect metallic layer over a portion of the surface of the polymer layer for coupling the bond pad to the surface of the polymer layer; and

(e) disposing at least one solder bump on the polymer layer, the solder bump being in registration with the metallic layer for coupling the solder bump to the bond pad,

wherein the step of monolithically applying the polymer is controlled to provide the polymer layer with a particular thickness that causes the at least one solder bump to have an effective thermal expansion coefficient, as modified by the polymer layer, substantially equal to the first thermal expansion coefficient.

8. The method according to claim 7, in which the step of applying the metallic layer comprises (i) applying a removable polymeric mask over the surface of the chip to define a surface region for application of the interconnect metallic layer;

and (ii) removing the polymeric mask once the interconnect metallic layer has been applied.

9. A method for preparing a plurality of semiconductor chips for mounting to at least one circuit substrate having a first thermal expansion coefficient, the method comprising the steps of:

(a) providing a plurality of semiconductor chips on a wafer, each of the plurality of semiconductor chips having an active side on one side of the wafer, thereby defining a plurality of active sides, wherein at least one bond pad is disposed on each active side to define a plurality of bond pads;

(b) monolithically applying a polymer layer over the wafer so that the polymer layer is disposed over the plurality of active sides and plurality of bond pads;

(c) removing portions of the polymer layer to expose the plurality of bond pads, the layer abutting the plurality of bond pads; and

(d) depositing metal over the wafer so that an interconnect metallic layer couples a portion of the surface of the polymer layer to the plurality of bond pads; and

(e) disposing a plurality of solder bumps on the interconnect metallic layer, wherein the at least one substrate has a first thermal expansion coefficient, and

wherein the step of monolithically applying the polymer is controlled to provide the polymer layer with a particular thickness that causes the at least one solder bump to have an effective thermal expansion coefficient, as modified by the polymer layer, substantially equal to the first thermal expansion coefficient.

10. The method of claim 9, further comprising a step of dicing the wafer to separate the plurality of semiconductor chips to provide individual semiconductor chips.

11. The method of claim 10 in which the step of dicing the wafer is performed before the step of disposing the plurality of solder bumps.

12. The method of claim 10 in which the step of dicing the wafer is performed after the step of disposing the plurality of solder bumps.