Method to prevent electrical shorts between adjacent metal lines

• US 6,831,016 B2
• Filed: 05/21/2002
• Issued: 12/14/2004
• Est. Priority Date: 09/04/2001
• Status: Expired due to Term

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Tsai, Tzu-Ching, Hsu, Ping
• Primary Examiner(s): CHEN, KIN CHAN
• Application Number:
  US10/153,347
• Publication Number:
  US 20030045108A1
• Time in Patent Office: 938 Days
• Field of Search: 438/700, 438/692, 438/693, 438/706, 438/712, 438/714, 438/720
• US Class Current: 438/692
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation

Abstract

A method to prevent electrical shorts between adjacent metal lines on a semiconductor substrate having an insulating layer with a pair of damascene structures connecting to the semiconductor substrate and a scratch on the upper surface of the insulating layer, between the damascene structures, is provided. A diffusion barrier layer is deposited on the damascene structures and the scratch. Then, a metal layer is formed to fill the damascene structures. Next, the metal is chemical-mechanically polished to form a metal line. Finally, the diffusion barrier layer disposed on the surface of the scratch is removed by etching process.

Claims

1. A method to prevent electrical shorts between adjacent metal lines, comprising the steps of:

(a) providing a semiconductor substrate;

(b) forming a gate oxide, a gate electrode and an etching stop layer, the etching stop layer being formed on the gate electrode;

(c) forming a first insulating layer on the semiconductor substrate and the etching stop layer;

(d) planarizing the first insulating layer until the etching stop layer is exposed;

(e) forming a second insulating layer on the first insulating layer, wherein the second insulating layer has a recess portion;

(f) selectively removing the second insulating layer and the first insulating layer to form a pair of dual damascene structures, the recess portion being located between the pair of dual damascene structures;

(g) conformally forming a diffusion barrier layer on the second insulating layer and the recess portion;

(h) forming a metal layer on the diffusion barrier layer to fill the pair of damascene structures;

(i) chemical mechanical polishing the metal layer to form a metal line; and

(l) removing the diffusion barrier layer disposed in the recess portion to expose the second insulating layer by etching.

2. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the second insulating layer is silicon oxide deposited by tetra-ethyl-ortho-silicate (TEOS).

3. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the diffusion barrier layer is a titanium nitride layer or a tantalum nitride layer.

4. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 3, wherein the metal layer is a tungsten layer.

5. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the etching process in step (l) is reactive ion etching (RIE).

6. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the diffusion barrier layer has an etching selectivity of about 6:

1 to about 7;

1 with respect to the metal line.

7. A method to prevent electrical shorts between adjacent metal lines as claimed in claim 1, wherein the etching process in step (l) uses an etching gas containing chlorine.