Multi-level memory cell with lateral floating spacers

• US 6,831,325 B2
• Filed: 12/20/2002
• Issued: 12/14/2004
• Est. Priority Date: 12/20/2002
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lojek, Bohumil
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US10/327,336
• Publication Number:
  US 20040119112A1
• Time in Patent Office: 725 Days
• Field of Search: 257/315, 257/320, 257/296, 257/314, 257/316
• US Class Current: 257/315
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A multi-level non-volatile memory transistor is formed in a semiconductor substrate. A conductive polysilicon control gate having opposed sidewalls is insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the spacers. Insulative material is placed over the structure with a hole cut above the control gate for contact by a gate electrode connected to, or part of, a conductive word line. Auxillary low voltage transistors which may be made at the same time as the formation of the memory transistor apply opposite phase clock pulses to source and drain electrodes so that first one side of the memory transistor may be written to, or read, then the other side.

Claims

1. A non-volatile memory transistor capable of storing two binary bits comprising:

a semiconductor substrate having an active region with spaced apart source and drain regions in the active region;

a first insulative layer disposed over the substrate;

a polysilicon gate disposed over the insulative layer, the polysilicon gate having sidewalls;

a pair of polysilicon upright spacers acting as charge storage regions spaced apart on opposite sides of the polysilicon gate adjacent to the sidewalls but separated therefrom and from the substrate by tunnel oxide;

a second insulative layer covering the upright spacers and the polysilicon gate, thereby allowing the spacers to be electrically floating structures;

a conductive layer over the second insulative layer and contacting the polysilicon gate through an opening in the second insulative layer, the conductive layer having a voltage supply associated therewith, thereby allowing the polysilicon gate to serve as a control gate; and

timing means for applying voltage alternately to one of the source and drain regions and then the other whereby each of the upright spacers may be independently read or written in cooperation with the voltage applied to the conductive layer.

2. The memory transistor of claim 1 wherein said timing means comprises a pair of opposite phase transistors connected to power supplies for first raising the level of one of the source and drain regions and then the other.

3. A non-volatile memory transistor capable of storing two binary bits comprising:

a semiconductor substrate having an active region with spaced apart source and drain regions in the active region;

a first insulative layer disposed over the substrate;

a conductive polysilicon gate disposed over the insulative layer, at least part of the polysilicon gate between the source and drain the polysilicon gate having sidewalls;

a pair of conductive polysilicon upright spacers acting as charge storage regions spaced apart on opposite sides of the polysilicon gate adjacent to the sidewalls but separated therefrom and from the substrate by tunnel oxide; and

timing means for applying voltage alternately to one of the source and drain regions and then the other whereby each of the upright spacers may be independently read or written by charge transfer to and from the polysilicon gate through the tunnel oxide.

4. In a memory array having rows and columns of memory cells, each memory cell having a non-volatile memory transistor capable of storing one of four memory states comprising:

a semiconductor substrate having an active region with spaced apart source and drain regions in the active region;

a first insulative layer disposed over the substrate;

a conductive polysilicon gate disposed over the insulative layer, at least part of the polysilicon gate between the source and drain, the polysilicon gate having sidewalls;

a pair of conductive polysilicon upright spacers acting as charge storage regions spaced apart on opposite sides of the polysilicon gate adjacent to the sidewalls but separated therefrom and from the substrate by tunnel oxide; and

means for applying voltage to each of the source and drain regions independently at different times whereby each of the upright spacers may be independently read or written alternately at different times whereby both spacers may be charged, or neither spacer charged, or either spacer charged giving rise to four memory states for each memory cell.