Data carrier with means for reducing the power consumption upon reception of data

• US 6,831,548 B1
• Filed: 08/11/1999
• Issued: 12/14/2004
• Est. Priority Date: 08/17/1998
• Status: Expired due to Term

• Current Assignee: Quotainne Enterprises LLC
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Eber, Wolfgang, Thüringer, Peter
• Primary Examiner(s): Zimmerman, Brian
• Assistant Examiner(s): NGUYEN, NAM V
• Application Number:
  US09/372,460
• Time in Patent Office: 1,952 Days
• Field of Search: 340/10.33, 340/10.44, 340/825.54, 340/10.52, 340/825.63, 455/343, 455/38.2, 370/311, 342/50, 342/51, 342/42
• US Class Current: 340/10.33
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A data carrier (1), or a circuit (2) for such a data carrier (1), which is arranged to receive a carrier signal (CSM) amplitude modulated in conformity with data (DA), is provided with data regenerating means (12) for regenerating data (DA) modulated on the amplitude modulated carrier signal (CSM), and with data processing means (28) for processing data (DA), the data regenerating means (12) additionally including receiving storage means (20) for temporarily storing a predetermined quantity of data (DA), and also detection means (22) for detecting the fact that the predetermined quantity of data (DA) has been buffered in the receiving storage means (20), the detection means (22) being capable of generating control information (CI1) whereby the data processing means (28) can be switched over from a power saving operating mode to a normal operating mode.

Claims

1. A data carrier (1) comprising:

receive means (3) for receiving a carrier signal (CSM);

voltage generating means (7), coupled to the receiver means (3), for generating a supply voltage (V) for the data carrier (1) using the carrier signal (CSM), said carrier signal (CSM) being amplitude modulated during a data receiving operation in dependence on data (DA) to be received, said amplitude modulation comprising high segments (H) of high amplitude and pause segments (P) of reduced amplitude, said voltage generating means (7) generating a reduced supply voltage during the data receiving operation due to the amplitude modulation; and

a circuit (2), coupled to the receiver means (3), said circuit comprising;

data regenerating means (12) whereto the received amplitude modulated carrier signal (CSM) can be applied during the data receiving operation, and whereby the data (DA) modulated on the carrier signal (CSM) can be regenerated, and

data processing means (28) whereto the regenerated data (DA) can be applied and whereby the regenerated data (DA) can be processed,

characterized in that

with the data regenerating means (12) there, are associated receiving storage means (20) which are constructed and arranged to store regenerated data (DA) in conformity with a given data quantity,

that the data regenerating means (12) additionally include detection means (22) which are capable of detecting the fact that regenerated data (DA) in conformity with the given data quantity has been regenerated by the data regenerating means (12) and stored by the receiving storage means (20), and whereby, upon detection of this fact, control information (CI1) can be generated and applied to the data processing means (28),

that the data processing means (28) are constructed so that they can be switched between a normal operating mode when the supply voltage (V) is available and a power saving operating mode when the reduced supply voltage is available,

that the data processing means (28) can be switched, in dependence on the control information (CI1), from their power saving operating mode to their normal operating mode, and

that the data processing means (28) are switched to their normal operating mode, the regenerated data (DA) stored in the receiving storage means (20) can be transferred to the data processing means (28).

2. A data carrier (1) as claimed in claim 1, characterized in that the receiving storage means (20) are arranged to store regenerated data (DA) in conformity with one bit.

3. A data carrier (1) as claimed in claim 2, characterized in that the receiving storage means (20) are formed by a flip-flop.

4. A data carrier (1) as claimed in claim 2, characterized in that the data processing means (28) are arranged to return automatically, after switching over from their power saving operating mode to their normal operating mode in dependence on the control information (CI1), to their power saving operating mode after a period of time long enough to ensure correct processing of one bit has elapsed.

5. A data carrier (1) as claimed in claim 1, characterized in that the receiving storage means (20) are arranged to store regenerated data (DA) in conformity with one byte.

6. A data carrier as claimed in claim 5, characterized in that the receiving storage means (20) are formed by a register for storing one byte.

7. A data carrier as claimed in claim 5, characterized in that the data processing means (28) are arranged to return automatically, after switching over from their power saving operating mode to their normal operating mode in dependence on the control information (CI1), to their power saving operating mode after a period of time long enough to ensure correct processing of one byte has elapsed.

8. A data carrier (1) as claimed in claim 1, characterized in that the receiving storage means (20) are arranged to store regenerated data (DA) in conformity with a data block consisting of a plurality of bytes.

9. A data carrier (1) as claimed in claim 8, characterized in that the receiving storage means (20) are formed by a part of a RAM (random access memory).

10. A data carrier (1) as claimed in claim 8, characterized in that the data processing means (28) are arranged to return automatically, after switching over from their power saving operating mode to their normal operating mode in dependence on the control information (CI1), to their power saving operating mode after a period of time long enough to ensure correct processing of a data block consisting of a plurality of bytes has elapsed.

11. A circuit (2) powered by a supply voltage generated using a carrier signal (CSM), said supply voltage being reduced during a data receiving operation due to amplitude modulation of the carrier signal, said circuit (2) comprising:

data regenerating means (12) to receive the amplitude modulated carrier signal (CSM) during the data receiving operation, said amplitude modulated carrier signal (CSM) being amplitude modulated in dependence on data (DA) to be received and consisting of high segments (H) of high amplitude and pause segments (P) of reduced amplitude, whereby the data (DA) modulated on the carrier signal (CSM) can be regenerated; and

data processing means (28) whereto the regenerated data (DA) can be applied and whereby the regenerated data (DA) can be processed,

characterized in that

with the data regenerating means (12) there are associated receiving storage means (20) which are constructed and arranged to store regenerated data (DA) in conformity with a given data quantity,

that the data regenerating means (12) additionally include detection means (22) which are capable of detecting the fact that regenerated data (DA) in conformity with the given data quantity has been regenerated by the data regenerating means (12) and stored by the receiving storage means (20), and whereby, upon detection of this fact, control information (CI1) can be generated and applied to the data processing means (28),

that the data processing means (28) are constructed so that they can be switched between a normal operating mode when the supply voltage is not reduced and a power saving operating mode when the supply voltage is reduced,

that the data processing means (28) can be switched, in dependence on the control information (CI1), from their power saving operating mode to their normal operating mode, and

that when the data processing means (28) are switched to their normal operating mode, the regenerated data (DA) stored in the receiving storage means (20) can be transferred to the data processing means (28).

12. A circuit (2) as claimed in claim 11, characterized in that the receiving storage means (20) are arranged to store regenerated data (DA) in conformity with one bit.

13. A circuit (2) as claimed in claim 12, characterized in that the receiving storage means (20) are formed by a flip-flop.

14. A circuit (2) as claimed in claim 12, characterized in that the data processing means (28) are arranged to return automatically, after switching over from their power saving operating mode to their normal operating mode in dependence on the control information (CI1), to their power saving operating mode after a period of time long enough to ensure correct processing of one bit has elapsed.

15. A circuit (2) as claimed in claim 11, characterized in that the receiving storage means (20) are arranged to store regenerated data (DA) in conformity with one byte.

16. A circuit (2) as claimed in claim 15, characterized in that the receiving storage means (20) are formed by a register for storing one byte.

17. A circuit (2) as claimed in claim 15, characterized in that the data processing means (28) are arranged to return automatically, after switching over from their power saving operating mode to their normal operating mode in dependence on the control information (CI1), to their power saving operating mode after a period of time long enough to ensure correct processing of one byte has elapsed.

18. A circuit (2) as claimed in claim 11, characterized in that the receiving storage means (20) are arranged to store regenerated data (DA) in conformity with a data block consisting of a plurality of bytes.

19. A circuit (2) as claimed in claim 18, characterized in that the receiving storage means (20) are formed by a part of a RAM.

20. A circuit arrangement (2) as claimed in claim 18, characterized in that the data processing means (28) are arranged to return automatically, after switching over from their power saving operating mode to their normal operating mode in dependence on the control information (CI1), to their power saving operating mode after a period of time long enough to ensure correct processing of a data block consisting of a plurality of bytes, has elapsed.

21. A method of receiving data in an IC data transponder including a processor, the method comprising:

detecting that an increment of data has been received, and providing a first signal to the processor to cause the processor to retrieve the increment of data;

repeating the preceding step some number of times;

detecting that a last increment of data has been received, and providing a second signal to the processor;

wherein the processor occupies a low power state, leaves the low power state in response to the first signal and in response to the second signal, and thereafter returns to the low power state.

22. An IC data transponder comprising:

a processor having a low power state;

a data receiver;

means for detecting that an increment of data has been received, and providing a first signal to the processor to cause the processor to retrieve the increment of data;

means for detecting that a last increment of data has been received, and providing a second signal to the processor;

wherein the processor occupies the low power state, leaves the low power state in response to the first signal and in response to the second signal, and thereafter returns to the low power state.