Synchronized image display and buffer swapping in a multiple display environment

• US 6,831,648 B2
• Filed: 11/27/2001
• Issued: 12/14/2004
• Est. Priority Date: 11/27/2000
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Mukherjee, Shrijeet, Sarcar, Kanoj, Tornes, James
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Monestime, Mackly
• Application Number:
  US09/993,925
• Publication Number:
  US 20020118201A1
• Time in Patent Office: 1,113 Days
• Field of Search: 345/502, 345/503, 345/504, 345/505, 345/506, 712/10, 712/11, 712/16, 712/19, 712/31, 709/208
• US Class Current: 345/504
• CPC Class Codes: G06F 3/1438 using more than one graphics controller
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Claims

1. A graphics system for generating synchronized images comprising:

a plurality of slave processors;

a master processor for synchronizing generation of a common scene by said plurality of slave processors;

a synchronization module associated with said master processor, wherein said synchronization module generates a time synchronization signal and an interrupt signal that suspends operation of each of said plurality of slave processors when a command is to be sent to reset each of said plurality of slave processors to start display of a next frame at approximately the same position;

a plurality of device drivers for exchanging synchronization commands between said master processor and said plurality of slave processors, each device driver being associated with one of said plurality of slave processors;

a timing signal provider for propagating a time synchronization signal to said plurality of slave processors from a synchronization signal generator associated with said master processor;

at least one graphics processor associated with each slave processor for producing pixels in synchronization with the time synchronization signal; and

a communications link connecting said master processor to each of said plurality of slave processors to provide simultaneous communication of a synchronization command to each of said plurality of slave processors.

2. The graphics system of claim 1, wherein said time synchronization signal is a pulse stream signal.

3. The graphics system of claim 2, wherein said pulse stream signal is a clock signal.

4. The graphics system of claim 2, wherein said pulse stream signal is a video signal.

5. The graphics system of claim 1, further comprising a connector for transmitting an electrical signal between said timing signal provider and said at least one graphics processor associated with each slave processor.

6. The graphics system of claim 5, wherein said timing signal provider is an integrated circuit board.

7. The graphics system of claim 5, wherein said timing signal provider is a fanout box having signal amplifiers.

8. The graphics system of claim 1, wherein said communications link is a multidrop cable.

9. The graphics system of claim 1, wherein said communications link is a daisy chain.

10. A method for image display synchronization, the method comprising the steps of:

(a) providing a time synchronization signal to each of a plurality of slave processors so that a plurality of graphics processors associated with said slave processors display pixels at approximately the same rate,

(b) issuing a first command from a master processor to said plurality of slave processors to disable interrupts to said plurality of graphics processors;

(c) polling by each of said plurality of slave processors for a second command to cause each of slave processors to execute a vertical retrace at a specified line; and

(d) issuing the second command from said master processor to said plurality of slave processors to cause each of said slave processors to execute vertical retrace at a specified line.

11. The method of claim 10, wherein said first and second commands are transmitted in a daisy-chained manner from slave processor to slave processor among the said plurality of slave processors.

12. The method of claim 11, further comprising the step of receiving said second command at each of said plurality of slave processors and, in response, resetting a digital to analog converter within each of said plurality of graphics processors to said specified line.

13. A graphics system for generating synchronized images comprising:

a plurality of slave processors;

a master processor for synchronizing generation of a common scene by said plurality of slave processors, wherein said master processor and at least one of said plurality of slave processors are located at multiple locations;

a synchronization module associated with said master processor, wherein said synchronization module generates a time synchronization signal and an interrupt signal that suspends operation of each of said plurality of slave processors when a command is to be sent to reset each of said plurality of slave processors to start display of a next frame at approximately the same position;

a plurality of device drivers for exchanging synchronization commands between said master processor and said plurality of slave processors, each device driver being associated with one of said plurality of slave processors;

a timing signal provider for propagating a time synchronization signal to said plurality of slave processors from a synchronization signal generator associated with said master processor;

at least one graphics processor associated with each slave processor for producing pixels in synchronization with the time synchronization signal; and

a communications link connecting said master processor to each of said plurality of slave processors to provide simultaneous communication of a synchronization command to each of said plurality of slave processors.

14. A graphics system for generating synchronized images comprising:

a plurality of slave processors;

a master processor for synchronizing generation of a common scene by said plurality of slave processors, wherein said master processor and at least one of said plurality of slave processors are located at multiple locations;

a synchronization module associated with said master processor, wherein said synchronization module generates a time synchronization signal and an interrupt signal that suspends operation of each of said plurality of slave processors when a command is to be sent to reset each of said plurality of slave processors to start display of a next frame at approximately the same position, wherein said synchronization module provides timing adjustments that account for transmission delays of signals between said master processor and said plurality of slave processors;

a plurality of device drivers for exchanging synchronization commands between said master processor and said plurality of slave processors, each device driver being associated with one of said plurality of slave processors;

a timing signal provider for propagating a time synchronization signal to said plurality of slave processors from a synchronization signal generator associated with said master processor;

at least one graphics processor associated with each slave processor for producing pixels in synchronization with the time synchronization signal;

a communications link connecting said master processor to each of said plurality of slave processors to provide simultaneous communication of a synchronization command to each of said plurality of slave processors;

a plurality of display devices, wherein each of said plurality of display devices is coupled to a corresponding graphics processor among said at least one graphics processor.

15. The graphics system of claim 14, wherein said plurality of display devices are coupled through an Internet.

16. The graphics system of claim 14, wherein said plurality of slave processors are coupled through an Internet.

17. A method of image display synchronization, the method comprising the steps of:

(a) providing a time synchronization signal to each of a plurality of slave processors so that a plurality of graphics processors associated with said slave processors display pixels at approximately the same rate,

(b) issuing a first command from a master processor to said plurality of slave processors to disable interrupts to said plurality of graphics processors;

(c) polling by each of said plurality of slave processors for a second command to cause each of slave processors to execute a vertical retrace at a specified line; and

(d) issuing a second command from said master processor to said plurality of slave processors to cause each of said slave processors to execute vertical retrace at a specified line; and

(e) synchronizing the display of images on multiple displays based on the time synchronization signal.

18. The method of claim 17, wherein step (a), providing a time synchronization signal occurs over an Internet.