Circuit and method for pixel rearrangement in a digital pixel sensor readout

• US 6,831,684 B1
• Filed: 08/15/2000
• Issued: 12/14/2004
• Est. Priority Date: 05/09/2000
• Status: Expired due to Term

• Current Assignee: Pixim, Inc. (Sony Group Corp.)
• Original Assignee: Pixim, Inc. (Sony Group Corp.)
• Inventors: Yang, David Xiao Dong, Ewedemi, Odutola Oluseye, Deng, Zhonghan John, Motta, Ricardo Jansson
• Primary Examiner(s): Vu, Ngoc-Yen, Vu, Ngoc-Yen
• Assistant Examiner(s): AGGARWAL, YOGESH K
• Application Number:
  US09/638,503
• Time in Patent Office: 1,582 Days
• Field of Search: 348/294, 348/222.1, 348/302, 348/303, 348/304, 348/305, 348/306, 348/307, 348/308, 348/309, 348/310
• US Class Current: 348/222.1
• CPC Class Codes: H04N 1/00307 with a mobile telephone apparatus constructional features of portable telephone sets H04M1/0202; mobile radio systems H04W84/00
• CPC Class Codes: H04N 2201/0068 Converting from still picture data
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 7/142 Constructional details of the terminal equipment, e.g. arrangements of the camera and the display

Abstract

An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

Claims

1. An image sensor, comprising:

a sensor array, including a two-dimensional array of digital pixels, each of said digital pixels outputting digital signals as digital pixel data in k bits, said sensor array outputting said k-bit digital pixel data representing an image of a scene, said digital pixel data being outputted in a sensor-bit arrangement where said k-bit digital pixel data are arranged in a bit plane format in k numbers of bit planes;

a data memory, in communication with said sensor array, for storing said k-bit digital pixel data in said sensor-bit arrangement; and

a pixel normalization circuit coupled to said data memory for rearranging said k-bit digital pixel data into a pixel-bit order and providing said rearranged pixel data as output signals, wherein said rearranged pixel data have all k bits of said digital pixel data associated with each digital pixel in a consecutive order.

2. The image sensor of claim 1, wherein said sensor array, said data memory and said pixel normalization circuit are fabricated in a single integrated circuit.

3. The image sensor of claim 1, wherein said pixel normalization circuit rearranges said digital pixel data through routing of signal lines between said data memory and said pixel normalization circuit.

4. The image sensor of claim 1, wherein said pixel normalization circuit rearranges said digital pixel data through hard-wiring of signal lines between said data memory and said pixel normalization circuit.

5. The image sensor of claim 1, wherein said rearranged pixel data are provided as output signals of said image sensor.

6. The image sensor of claim 1, wherein said rearranged pixel data are written into said data memory.

7. The image sensor of claim 1, wherein said rearranged pixel data has k bits of a first digital pixel in a consecutive order followed by k bits of a second digital pixel.

8. The image sensor of claim 1, wherein said pixel normalization circuit comprises a buffer for storing a portion of said digital pixel data from said data memory, and said pixel normalization circuit rearranges said digital pixel data by routing of signal lines between said data memory and said buffer.

9. The image sensor of claim 1, wherein said data memory is of N by M by k bits and said data memory stores said digital pixel data in a bit-plane format by storing a first bit of digital pixel data outputted by each of said digital pixels consecutively, followed by a second bit of digital pixel data outputted by each of said digital pixels.

10. The image sensor of claim 9, wherein said rearranged pixel data has k bits of digital pixel data of a first digital pixel in a consecutive bit order followed by k bits of digital pixel data of a second digital pixel in a consecutive bit order.

11. The image sensor of claim 10, wherein said first digital pixel and said second digital pixel are not adjacent digital pixels in said sensor array.

12. A method in an image sensor, comprising:

capturing an image of a scene using a sensor array, said sensor array including a two-dimensional array of digital pixels, said digital pixels outputting digital signals as digital pixel data in k bits representing the image of the scene;

outputting said digital pixel data in a sensor-bit order where said k-bit digital pixel data are arranged in a bit plane format in k number of bit planes;

storing said digital pixel data in a data memory; and

rearranging said digital pixel data into a pixel-bit order, wherein all k bits of said digital pixel data associated with each digital pixel are in a consecutive order.

13. The method of claim 12, further comprising:

storing said rearranged pixel data in said data memory.

14. The method of claim 12, further comprising:

providing said rearranged pixel data as output signals from said image sensor.

15. The method of claim 12, wherein said act of rearranging said pixel data is performed by routing of signal lines.