Filter cell, method of deriving an echo component and an echo canceling system employing the same

• US 6,831,900 B2
• Filed: 02/09/2001
• Issued: 12/14/2004
• Est. Priority Date: 02/09/2001
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Blake, Roy B.
• Primary Examiner(s): MARCELO, MELVIN C
• Application Number:
  US09/780,661
• Publication Number:
  US 20020150059A1
• Time in Patent Office: 1,404 Days
• Field of Search: 370/286-292, 379/406-1-4
• US Class Current: 370/289
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers

Abstract

A filter cell, method of deriving an echo component and an echo canceling system, bit pump and transceiver employing the same. In one embodiment, the filter cell includes a first summing node that receives a first input based on a signal sample that contains an echo component of an echo. The filter cell also includes a second summing node that receives a second input based on the signal sample. The filter cell still further includes a multiplier that employs outputs from the first and second summing nodes and a scaling factor to derive first and second outputs containing a remnant of the echo component.

Claims

1. A filter cell, comprising:

a first summing node configured to receive a first input based on a signal sample that contains an echo component of an echo;

a second summing node configured to receive a second input based on said signal sample; and

a multiplier configured to employ outputs from said first and second summing nodes and a scaling factor to derive first and second outputs containing a remnant of said echo component.

2. The filter cell as recited in claim 1 further comprising a delay element interposed between said first and second summing nodes.

3. The filter cell as recited in claim 1 wherein said scaling factor is a pole value associated with said filter cell.

4. The filter cell as recited in claim 1 wherein said filter cell is a single-pole all-pass filter cell.

5. The filter cell as recited in claim 1 wherein said filter cell forms a portion of a Laguerre infinite impulse response filter.

6. A method of deriving a remnant of an echo component, comprising:

receiving a first input based on a signal sample that contains an echo component of an echo at a first summing node;

receiving a second input based on said signal sample at a second summing node; and

employing outputs from said first and second summing nodes and a scaling factor at a multiplier to derive first and second outputs containing a remnant of said echo component.

7. The method as recited in claim 6 further comprising providing a delay element between said first and second summing nodes.

8. The method as recited in claim 6 wherein said scaling factor is a pole value.

9. The method as recited in claim 6 wherein said method is performed by a single-pole all-pass filter cell.

10. The method as recited in claim 6 wherein said method is performed by a filter cell forming a portion of a Laguerre infinite impulse response filter.

11. An echo canceling system, coupled between a transmit and receive path of a bit pump, that receives and attenuates an echo in a receive signal propagating along said receive path, comprising:

a slave echo canceling stage that employs a filter coefficient to attenuate said echo;

a separation circuit, coupled to said slave echo canceling stage, that generates data representing a residual echo substantially exclusive of said receive signal; and

a master echo canceling stage, coupled to said separation circuit, that receives said data and includes a Laguerre infinite impulse response filter with a filter cell, including;

a first summing node that receives a first input based on a signal sample that contains an echo component of said data,

a second summing node that receives a second input based on said signal sample, and

a multiplier that employs outputs from said first and second summing nodes and a scaling factor to derive first and second outputs containing a remnant of said echo component, said master echo canceling stage modifying said filter coefficient based thereon.

12. The echo canceling system as recited in claim 11 wherein said filter cell further comprises a delay element interposed between said first and second summing nodes.

13. The echo canceling system as recited in claim 11 wherein said scaling factor is a pole value associated with said filter cell.

14. The echo canceling system as recited in claim 11 wherein said filter cell is a single-pole all-pass filter cell.

15. The echo canceling system as recited in claim 11 wherein said separation circuit comprises an equalizer/slicer stage that determines a symbol associated with said receive signal, said separation circuit further comprising an estimator stage, coupled to said equalizer/slicer stage, that employs said symbol and develops an estimated receive signal.

16. A bit pump having a transmit and receive path, comprising:

a precoder, coupled to said transmit path, that preconditions a transmit signal propagating along said transmit path;

a modulator, coupled to said precoder, that reduces a noise associated with said transmit signal;

an analog-to-digital converter, coupled to said receive path, that converts a receive signal received at said bit pump into a digital format;

a decimator, coupled to said analog-to-digital converter, that downsamples said receive signal propagating along said receive path; and

an echo canceling system, coupled between said transmit and receive path of said bit pump, that receives and attenuates an echo in said receive signal propagating along said receive path, including;

a slave echo canceling stage that employs a filter coefficient to attenuate said echo,

a separation circuit, coupled to said slave echo canceling stage, that generates data representing a residual echo substantially exclusive of said receive signal, and

a master echo canceling stage, coupled to said separation circuit, that receives said data and includes a Laguerre infinite impulse response filter with a filter cell, including;

a first summing node that receives a first input based on a signal sample that contains an echo component of said data,

a second summing node that receives a second input based on said signal sample, and

a multiplier that employs outputs from said first and second summing nodes and a scaling factor to derive first and second outputs containing a remnant of said echo component, said master echo canceling stage modifying said filter coefficient based thereon.

17. The bit pump as recited in claim 16 wherein said filter cell further comprises a delay element interposed between said first and second summing nodes.

18. The bit pump as recited in claim 16 wherein said scaling factor is a pole value associated with said filter cell.

19. The bit pump as recited in claim 16 wherein said filter cell is a single-pole all-pass filter cell.

20. The bit pump as recited in claim 16 wherein said separation circuit comprises an equalizer/slicer stage that determines a symbol associated with said receive signal, said separation circuit further comprising an estimator stage, coupled to said equalizer/slicer stage, that employs said symbol and develops an estimated receive signal.

21. A transceiver, comprising:

a framer that formats signals within said transceiver;

a bit pump coupled to said framer and having a transmit and receive path, including;

a precoder, coupled to said transmit path, that preconditions a transmit signal propagating along said transmit path;

a modulator, coupled to said precoder, that reduces a noise associated with said transmit signal;

an analog-to-digital converter, coupled to said receive path, that converts a receive signal received at said bit pump into a digital format;

a decimator, coupled to said analog-to-digital converter, that downsamples said receive signal propagating along said receive path; and

an echo canceling system, coupled between said transmit and receive path of said bit pump, that receives and attenuates an echo in said receive signal propagating along said receive path, including;

a slave echo canceling stage that employs a filter coefficient to attenuate said echo,

a separation circuit, coupled to said slave echo canceling stage, that generates data representing a residual echo substantially exclusive of said receive signal, and

a master echo canceling stage, coupled to said separation circuit, that receives said data and includes a Laguerre infinite impulse response filter with a filter cell, including;

a first summing node that receives a first input based on a signal sample that contains an echo component of said data,

a second summing node that receives a second input based on said signal sample, and

a multiplier that employs outputs from said first and second summing nodes and a scaling factor to derive first and second outputs containing a remnant of said echo component, said master echo canceling stage modifying said filter coefficient based thereon; and

a controller that controls an operation of said framer and said bit pump.

22. The transceiver as recited in claim 21 wherein said filter cell further comprises a delay element interposed between said first and second summing nodes.

23. The transceiver as recited in claim 21 wherein said scaling factor is a pole value associated with said filter cell.

24. The transceiver as recited in claim 21 wherein said filter cell is a single-pole all-pass filter cell.

25. The transceiver as recited in claim 21 wherein said separation circuit comprises an equalizer/slicer stage that determines a symbol associated with said receive signal, said separation circuit further comprising an estimator stage, coupled to said equalizer/slicer stage, that employs said symbol and develops an estimated receive signal.