System and method of dual mode automatic gain control for a digital radio receiver

• US 6,831,957 B2
• Filed: 03/14/2001
• Issued: 12/14/2004
• Est. Priority Date: 03/14/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chen, Zhiliang Julian
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US09/805,825
• Publication Number:
  US 20020168037A1
• Time in Patent Office: 1,371 Days
• Field of Search: 375/316, 375/326, 375/327, 375/339, 375/344, 375/345, 455/196.1, 455/131, 455/182.1, 455/138, 455/139, 455/130, 455/232.1, 455/234.1, 455/252, 455/255, 455/257, 455/263
• US Class Current: 375/345
• CPC Class Codes: H03G 3/002 Control of digital or coded signals H03G3/3089 take precedence
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals
• CPC Class Codes: H04H 2201/20 digital audio broadcasting [DAB]

Abstract

A digital radio receiver system uses a dual mode automatic gain control architecture and method to enhance signal-to-noise ratio and linearity to accommodate reception and processing of both L-band RF signals and band-III RF signals. The system architecture employs an analog AGC to control high/low gain switches associated with front end low noise amplifiers and down converters, as well as a digital AGC to control gain controlled amplifier and programmable gain amplifier gain settings. The AGC control can be implemented totally within the system architecture or optionally can be implemented via an external data processing device such as a DSP or micro-controller.

Claims

1. A method of implementing dual mode automatic gain control for a digital radio receiver, the method comprising the steps of:

(a) providing a RF broadcast receiver having an IF gain controlled amplifier (GCA), a programmable gain amplifier (PGA), a digital automatic gain control (AGC) configured to control GCA gain and PGA gain in response to at least a digital output code that is determined partially by PGA output signal strength, at least one low noise amplifier (LNA), at least one down converter (Mixer), and an analog AGC configured to control LNA gain and Mixer gain in response to at least a GCA input signal;

(b) providing a gain control register having a LNA control bit, a Mixer control bit, a GCA control bit, and a PGA control bit;

(c) resetting the gain control register bits to an initial state; and

(d) adjusting LNA gain and Mixer gain via the analog AGC in response to the control register bit setting and the GCA input signal and further adjusting GCA gain and PGA gain via the digital AGC in response to the control register bit setting and the digital output code such that the LNA gain, Mixer gain, GCA gain and PGA gain combine to render the RF broadcast receiver capable of maximizing its signal-to-noise ratio and linearity to accommodate reception and amplification of L-band signals and band-III signals.

2. The method of implementing dual mode automatic gain control for a digital radio receiver according to claim 1 further comprising the steps of:

(e) adjusting the gain control register bits to a state determined by LNA gain, Mixer gain, GCA gain and PGA gain; and

(f) repeating steps (d) and (e) for a desired period of time.

3. The method of implementing dual mode automatic gain control according to claim 1 wherein the step (d) of adjusting LNA gain, Mixer gain, GCA gain and PGA gain further comprises the steps of:

implementing a first algorithmic gain decision procedure when the gain control register bits are all set to one;

implementing a second algorithmic gain decision procedure when the gain control register LNA and Mixer bits are set to one and the gain control register GCA and PGA bits are set to zero;

implementing a third algorithmic gain decision procedure when the gain control register LNA bit is set to one and the gain control register Mixer, GCA and PGA bits are set to zero; and

implementing a fourth algorithmic gain decision procedure when the gain control register bits are all set to zero.

4. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a first algorithmic gain decision procedure when the gain control register bits are all set to one comprises the step of setting the Mixer gain low, the GCA gain to its maximum, the PGA gain to its minimum, and leaving the LNA gain unchanged when the GCA input signal exceeds a predetermined voltage level.

5. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a first algorithmic gain decision procedure when the gain control register bits are all set to one comprises the step of leaving the LNA gain, the Mixer gain, the GCA gain and the PGA gain unchanged when the GCA input signal does not exceed a predetermined voltage level and the digital output code is equal to a predetermined code value.

6. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a first algorithmic gain decision procedure when the gain control register bits are all set to one comprises the step of leaving the LNA gain, the Mixer gain, the GCA gain and the PGA gain unchanged when the GCA input signal does not exceed a predetermined voltage level, the digital output code is less than a predetermined code value, and the PGA gain is set to its maximum value.

7. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a first algorithmic gain decision procedure when the gain control register bits are all set to one comprises the step of leaving the LNA gain, the Mixer gain and the GCA gain unchanged and adjusting the PGA gain to its maximum when the GCA input signal does not exceed a predetermined voltage level, the digital output code is less than a predetermined code value, the GCA gain is set to its maximum, and the PGA gain is not set at its maximum.

8. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a first algorithmic gain decision procedure when the gain control register bits are all set to one comprises the step of leaving the LNA gain, the Mixer gain and the GCA gain unchanged and adjusting the PGA gain to its minimum when the GCA input signal does not exceed a predetermined voltage level, the digital output code is greater than a predetermined value, the GCA gain is set to its maximum, and the PGA gain is not set at its minimum.

9. The method of implementing dual mode automatic gain control according to claim 4 wherein the step of implementing a first algorithmic gain decision procedure when the gain control register bits are all set to one comprises the step of leaving the LNA gain, the Mixer gain, the GCA gain and the PGA gain unchanged when the GCA input signal does not exceed a predetermined voltage level, the digital output code is greater than a predetermined code value, and the GCA gain and PGA gain are each set to its respective minimum.

10. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a second algorithmic gain decision procedure when the gain control register LNA and Mixer bits are set to one and the gain control register GCA and PGA bits are set to zero comprises the step of leaving the LNA gain unchanged, setting the Mixer gain low, setting the PGA gain to its minimum, and setting the GCA gain to a first predetermined GCA gain level when the GCA input signal exceeds a predetermined voltage level.

11. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a second algorithmic gain decision procedure when the gain control register LNA and Mixer bits are set to one and the gain control register GCA and PGA bits are set to zero comprises the step of leaving the LNA gain, the Mixer gain, the PGA gain, and the GCA gain unchanged when the GCA input signal does not exceed a predetermined voltage level and the digital output code is equal to a predetermined code value.

12. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a second algorithmic gain decision procedure when the gain control register LNA and Mixer bits are set to one and the gain control register GCA and PGA bits are set to zero comprises the step of leaving the LNA gain, the Mixer gain, the PGA gain, and the GCA gain unchanged when the GCA input signal does not exceed a predetermined voltage level, the digital output code is greater than a predetermined code value, and the PGA gain and GCA gain are each set to its respective minimum value.

13. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a second algorithmic gain decision procedure when the gain control register LNA and Mixer bits are set to one and the gain control register GCA and PGA bits are set to zero comprises the step of leaving the LNA gain, the Mixer gain, the PGA gain, and the GCA gain unchanged when the GCA input signal does not exceed a predetermined voltage level, the digital output code is less than a predetermined value, and the PGA gain and GCA gain are each set to their respective maximum values.

14. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a second algorithmic gain decision procedure when the gain control register LNA and Mixer bits are set to one and the gain control register GCA and PGA bits are set to zero comprises the step of leaving the LNA gain and the Mixer gain, and adjusting the GCA gain to its maximum when the GCA input signal does not exceed a predetermined voltage level, the digital output code is less than a predetermined code value, and the PGA gain is set to its minimum value.

15. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a second algorithmic gain decision procedure when the gain control register LNA and Mixer bits are set to one and the gain control register GCA and PGA bits are set to zero comprises the step of leaving the LNA gain and the Mixer gain, and adjusting the GCA gain to its minimum when the GCA input signal does not exceed a predetermined voltage level, the digital output code is greater than a predetermined code value, and the PGA gain is set to its maximum value.

16. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a third algorithmic gain decision procedure when the gain control register LNA bit is set to one and the gain control register Mixer bits, GCA bits and PGA bits are set to zero comprises the step of setting the LNA gain low, setting the Mixer gain low, setting the GCA gain at a predetermined GCA gain value, and setting the PGA gain at its minimum value when the GCA input signal exceeds a predetermined voltage level.

17. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a third algorithmic gain decision procedure when the gain control register LNA bit is set to one and the gain control register Mixer, GCA and PGA bits are set to zero comprises the step of leaving the LNA gain and the GCA gain unchanged when the GCA input signal exceeds a predetermined voltage level, the digital output code is equal to a predetermined code value, the Mixer gain is set to its minimum, the PGA gain is set to its minimum, and the GCA gain is set to its minimum.

18. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a third algorithmic gain decision procedure when the gain control register LNA bit is set to one and the gain control register Mixer, GCA and PGA bits are set to zero comprises the step of leaving the LNA gain and the GCA gain unchanged when the GCA input signal exceeds a predetermined voltage level, the digital output code is more than a predetermined code value, the Mixer gain is set to its minimum, the PGA gain is set to its minimum, and the GCA gain is set to its minimum.

19. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a third algorithmic gain decision procedure when the gain control register LNA bit is set to one and the gain control register Mixer, GCA and PGA bits are set to zero comprises the step of leaving the LNA gain unchanged, setting the Mixer gain low, setting the PGA gain low, and adjusting the GCA gain to its minimum when the GCA input signal exceeds a predetermined voltage level and the digital output code is more than a predetermined code value.

20. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a third algorithmic gain decision procedure when the gain control register LNA bit is set to one and the gain control register Mixer, GCA and PGA bits are set to zero comprises the step of leaving the LNA gain unchanged, setting the Mixer gain low, setting the PGA gain low, and adjusting the GCA gain to its maximum when the GCA input signal exceeds a predetermined voltage level, the digital output code is less than a predetermined code value, and the GCA gain is not at its maximum.

21. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a third algorithmic gain decision procedure when the gain control register LNA bit is set to one and the gain control register Mixer, GCA and PGA bits are set to zero comprises the step of leaving the LNA gain unchanged, setting the Mixer gain high, setting the PGA gain low, and setting the GCA gain to a predetermined level less than its maximum when the GCA input signal exceeds a predetermined voltage level, the digital output code is less than a predetermined code value, and the GCA gain is at its maximum.

22. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a fourth algorithmic gain decision procedure when the gain control register LNA, Mixer, GCA and PGA bits are set to zero comprises the step of leaving the LNA gain, the Mixer gain, the GCA gain, and the PGA gain unchanged when the digital output code is more than a predetermined code value, and the GCA gain is at its minimum.

23. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a fourth algorithmic gain decision procedure when the gain control register LNA, Mixer, GCA and PGA bits are set to zero comprises the step of leaving the LNA gain, the Mixer gain, the GCA gain, and the PGA gain unchanged when the digital output code is equal to a predetermined code value.

24. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a fourth algorithmic gain decision procedure when the gain control register LNA, Mixer, GCA and PGA bits are set to zero comprises the step of leaving the LNA gain, the Mixer gain, and the PGA gain unchanged, and adjusting the GCA gain to its minimum when the digital output code is more than a predetermined code value, and the GCA gain is not at its minimum.

25. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a fourth algorithmic gain decision procedure when the gain control register LNA, Mixer, GCA and PGA bits are set to zero comprises the step of leaving the LNA gain, the Mixer gain, the GCA gain, and the PGA gain unchanged, and adjusting the GCA gain to its maximum when the digital output code is less than a predetermined code value, and the GCA gain is not at its maximum.

26. The method of implementing dual mode automatic gain control according to claim 3 wherein the step of implementing a fourth algorithmic gain decision procedure when the gain control register LNA, Mixer, GCA and PGA bits are set to zero comprises the step of leaving the Mixer gain and PGA gain unchanged, setting the GCA gain to a predetermined level less than its maximum, and setting the LNA gain to its maximum when the digital output code is less than a predetermined code value, and the GCA gain is at its maximum.

27. A digital radio receiver comprising:

a IF gain controlled amplifier (GCA) having a variable gain;

a programmable gain amplifier (PGA) having a variable gain;

at least one low noise amplifier (LNA) having a variable gain;

at least one down converter (Mixer) having a variable gain;

a digital automatic gain control (AGC); and

a gain control register bit map having a GCA control bit, a PGA control bit, a LNA control bit, and a Mixer control bit, wherein the AGC is responsive to the gain control register bit map to enable a plurality of AGC states such that the digital radio receiver can maximize its signal-to-noise ratio and linearity to accommodate reception and amplification of L-band signals and band-III signals.

28. The digital radio receiver according to claim 27 wherein the plurality of AGC states is determined in response to the PGA gain, the LNA gain, the Mixer gain and the AGC gain.

29. The digital radio receiver according to claim 27 wherein the plurality of AGC states comprise:

a first gain stage when the gain control register bits are all set to a first state;

a second gain stage when the gain control register bits are all set to a second state;

a third gain stage when the gain control register bits are all set to a third state; and

a fourth gain stage when the gain control register bits are all set to a fourth state.

30. The digital radio receiver according to claim 29 wherein the first state is implemented when the gain control register bits are all set to one, the second state is implemented when the gain control register LNA and Mixer bits are set to one and the gain control register GCA and PGA bits are set of zero, the third state is implemented when the gain control register LNA bit is set to one and the gain control register Mixer, GCA and PGA bits are set to zero, and the fourth state is implemented when the gain control register bits are all set to zero.