Virtualization of computer system interconnects

• US 6,832,270 B2
• Filed: 03/08/2002
• Issued: 12/14/2004
• Est. Priority Date: 03/08/2002
• Status: Expired due to Term

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Das Sharma, Debendra, Gupta, Ashish
• Primary Examiner(s): Dang, Khanh
• Application Number:
  US10/092,603
• Publication Number:
  US 20040078647A1
• Time in Patent Office: 1,012 Days
• Field of Search: 710/3, 710/4, 710/9, 710/14-19, 710/36, 710/38, 710/51, 710/260, 710/306, 710/312, 710/314, 714/3-8, 370/227, 370/228
• US Class Current: 710/15
• CPC Class Codes: G06F 11/2005 using redundant communication controllers

Abstract

A virtual input/output (I/O) interconnect mechanism, and a corresponding method, for use in a computer system having a plurality of I/O devices and a plurality of processing units, where I/O devices and processing units are coupled by one or more bridge units, includes an address decode block having a multiplexer that multiplexes inputs to produce an address, where the address relates to a transaction related to a processor unit, a range register decoder that receives the address and provides a destination address of a module to receive the transaction related to the address, and a reroute module identification block that receives the destination address. The reroute module identification block, includes an original module identification that provides an address of one or more original modules in the computer system, and a remapped module identification that provides logical destination module identifications of substitute modules in the computer system, where a substitute module replaces functions of an original module in the computer system.

Claims

1. A virtual input/output (I/O) interconnect mechanism for use in a computer system having a plurality of I/O devices and a plurality of processing units, wherein I/O devices and processing units are coupled by one or more bridge units, the mechanism comprising:

an address decode block, comprising;

a multiplexer that multiplexes inputs to produce an address, wherein the address relates to a transaction related to a processor unit,

a range register decoder that receives the address and provides a destination address of a module to receive the transaction related to the address, and

a reroute module identification block that receives the destination address, the reroute module identification block, comprising;

an original module identification that provides an address of one or more original modules in the computer system, and

a remapped module identification that provides logical destination module identifications of substitute modules in the computer system, wherein a substitute module replaces functions of an original module in the computer system.

2. The mechanism of claim 1, wherein the reroute module identification block further comprises a valid bit indication, the valid bit indication indicating when a translation from the original module to the substitute module is valid.

3. The mechanism of claim 1, wherein the inputs received by the multiplexer are inputs from the plurality of I/O devices.

4. The mechanism of claim 1, wherein the address is an I/O device address.

5. The mechanism of claim 1, wherein the destination address is an address of one of the one or more bridge units.

6. The mechanism of claim 1, wherein the original module and the substitute module are a same type of device.

7. The mechanism of claim 6, wherein the original module and the substitute module are I/O devices.

8. The mechanism of claim 7, wherein the I/O devices are ethernet cards.

9. The mechanism of claim 1, wherein the substitute module comprises programming to claim transactions addressed to the original module.

10. The mechanism of claim 1, wherein a state of the original module is copied to the substitute module.

11. The mechanism of claim 1, wherein the substitute module is an inactive component of the computer system.

12. The mechanism of claim 1, wherein the substitute module is an active component of the computer system.

13. A method for rerouting a transaction along a virtual path from an original module in a computer system to a substitute module in the computer system, wherein a transaction is initiated to the original module, and wherein the original module has failed, the method, comprising:

storing a remapped module identification that identifies the substitute module as a substitute for the failed original module;

receiving a transaction for the failed original module, the transaction including an address of the failed original module;

extracting the address;

decoding the address to provide an identification of the failed original module for receipt of the transaction;

comparing the identification of the failed original module to the remapped module identification; and

rerouting the transaction to the substitute module based on the remapped module identification.

14. The method of claim 13, wherein the original module and the substitute module are input/output (I/O) devices.

15. The method of claim 14, wherein the I/O devices are ethernet cards.

16. The method of claim 13, wherein the substitute module is an active component of the computer system.

17. The method of claim 13, wherein the substitute module is an inactive component of the computer system.

18. The method of claim 13, further comprising copying a state of the failed original module to the substitute module.

19. The method of claim 13, further comprising reprogramming the substitute module to claim transactions addressed to the failed original module.

20. The method of claim 13, further comprising setting a valid bit to indicate if a translation from the original module to the substitute module is valid.

21. A method for creating a virtual hardware path in a computer system, comprising:

identifying a failed module in the computer system;

identifying a substitute module in the computer system, the substitute module capable of replacing the failed module;

storing an identification of the failed module and an identification of the substitute module, wherein the failed module identification is related to the substitute module identification;

programming the substitute module to receive transactions addressed to the failed module.

22. The method of claim 21, wherein programming the substitute module comprises:

copying a state of the failed module to the substitute module; and

programming the substitute module to claim the transactions addressed to the failed module.

23. An apparatus that creates a virtual hardware path in a computer system, comprising:

a reroute module identification block, comprising;

an original module identification section, and

a substitute module identification section, wherein an identification for a failed original module is entered into a space in the original module identification section and an identification for a substitute module is entered in to a space, corresponding to the space in the original module identification section, in the substitute module section; and

programming adapted to the substitute module, wherein the substitute module is reprogrammed to claim transactions addressed to the failed original module and to copying a state of the failed original module to the substitute module.

24. A method for substituting operating components for failed components in a computer system, comprising:

detecting a failed component;

determining if a component of a same type as the failed component exists; and

if a substitute component exists;

suspending activities to the failed component,

copying a state of the failed component to the substitute component,

deconfiguring the failed component,

updating reroute module identification to remap the failed component to the substitute component,

updating configuration registers of the substitute component, and

resuming activities to the failed component.

25. The method of claim 24, wherein a substitute component does not exist, the method further comprising invoking an error handler.

26. The method of claim 24, wherein the activities include direct memory access.