Microprocessor with repeat prefetch instruction

• US 6,832,296 B2
• Filed: 04/09/2002
• Issued: 12/14/2004
• Est. Priority Date: 04/09/2002
• Status: Active Grant

• Current Assignee: IP-First LLC
• Original Assignee: IP-First LLC
• Inventors: Hooker, Rodney E.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Li, Zhuo H.
• Application Number:
  US10/119,435
• Publication Number:
  US 20030191900A1
• Time in Patent Office: 980 Days
• Field of Search: 711/137, 711/117-118, 711/123, 711/125, 711/213, 711/122, 711/133, 710/107, 709/203, 712/238
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preceded by the REP string instruction prefix. The programmer specifies the count of cache lines to be prefetched in the ECX register, similarly to the repeat count of a REP string instruction. The effective address of the first cache line is specified similar to the conventional PREFETCH instruction. The REP PREFETCH instruction stops if the address of the current prefetch cache line misses in the TLB, or if the current processor level changes. Additionally, a line is prefetched only if the number of free response buffers is above a programmable threshold. The prefetches are performed at a lower priority than other activities needing access to the cache or TLB.

Claims

1. A microprocessor for executing a prefetch instruction specifying a block of cache lines to be prefetched from a System memory into a cache of the microprocessor, the microprocessor comprising:

a prefetch count register, for storing a count of the cache lines remaining to be prefetched;

a general purpose register, coupled to said prefetch count register, for storing an initial value of said count, said initial value loaded into said general purpose register by an instruction prior to the prefetch instruction;

control logic, coupled to said prefetch count register, for copying said initial value from said general purpose register to said prefetch count register in response to decoding the prefetch instruction; and

a comparator, coupled to said control logic, for determining whether a number of free response buffers in the microprocessor is greater than a threshold value;

wherein said control logic delays prefetching the cache lines until said number of free response buffers is greater than said threshold value, wherein said threshold value is programmable.

2. The microprocessor of claim 1, wherein said programmable threshold value is programmable by a program executing on the microprocessor.

3. The microprocessor of claim 1, wherein said programmable threshold value is programmable by an external input to the microprocessor.

4. A microprocessor for executing a prefetch instruction specifying a block of cache lines to be prefetched from a system memory into a cache of the microprocessor, the microprocessor comprising:

a prefetch count register, for storing a count of the cache lines remaining to be prefetched;

a general purpose register, coupled to said prefetch count register, for storing an initial value of said count, said initial value loaded into said general purpose register by an instruction prior to the prefetch instruction;

control logic, coupled to said prefetch count register, for copying said initial value from said general purpose register to said prefetch count register in response to decoding the prefetch instruction;

a comparator, coupled to said control logic, for determining whether a number of free response buffers in the microprocessor is greater than a threshold value; and

a replay buffer, coupled to said control logic, for storing state associated with the prefetch instruction if said number of free response buffers is not greater than said threshold value.

5. The microprocessor of claim 4, wherein said control logic is configured to resume prefetching of the cache lines after said number of free response buffers becomes greater than said threshold value.

6. A microprocessor in a system with a system memory, the microprocessor comprising:

an instruction decoder, for decoding a prefetch instruction specifying a count of cache lines to prefetch from the system memory and an address in the system memory of said cache lines;

an address, register, coupled to said instruction decoder, for storing said address specified in said prefetch instruction;

a count register, coupled to said instruction decoder, for storing said count specified in said prefetch instruction;

control logic, coupled to said address register, configured to control the microprocessor to prefetch said cache lines specified in said address register and said count register from the system memory into a cache memory of the microprocessor; and

an address generator, coupled to said address register, for generating said address stored in said address register based on operands specified by said prefetch instruction;

wherein said operands specified by said prefetch instruction are specified in one or more registers of a register file of the microprocessor, wherein said operands specified in said one or more registers is specified in a segment;

offset format substantially conforming to a Pentium III architecture segment;

offset format.

7. The microprocessor of claim 6, wherein said one or more registers substantially conform to Pentium III DS:

ESI registers.

8. A microprocessor in a system with a system memory, the microprocessor comprising:

an instruction decoder, for decoding a prefetch instruction specifying a count of cache lines to prefetch from the system memory and an address in the system memory of said cache lines;

an address register, coupled to said instruction decoder, for storing said address specified in said prefetch instruction;

a count register, coupled to said instruction decoder, for storing said count specified in said prefetch instruction; and

control logic, coupled to said address register, configured to control the microprocessor to prefetch said cache lines specified in said address register and said count register from the system memory into a cache memory of the microprocessor;

wherein said control logic stops prefetching said cache lines if the microprocessor changes its current privilege level to a more privileged privilege level.

9. The microprocessor of claim 8, wherein said control logic stops prefetching said cache lines if the microprocessor changes its current privilege level to a privilege level substantially conforming to a Pentium III architecture ring 0 privilege level.

10. A microprocessor in a system with a system memory, the microprocessor comprising:

an instruction decoder, for decoding a prefetch instruction specifying a count of cache lines to prefetch from the system memory and an address in the system memory of said cache lines;

an address register, coupled to said instruction decoder, for storing said address specified in said prefetch instruction;

a count register, coupled to said instruction decoder, for storing said count specified in said prefetch instruction; and

control logic, coupled to said address register, configured to control the microprocessor to prefetch said cache lines specified in said address register and said count register from the system memory into a cache memory of the microprocessor;

wherein said control logic decrements said count stored in said count register without prefetching one of said cache lines specified by said address stored in said address register if said address hits in said cache memory, wherein said control logic increments said address stored in said address register if said address hits in said cache memory.

11. A method of a microprocessor prefetching cache lines into its cache, the method comprising:

(a) detecting a repeat prefetch instruction specifying a count of cache lines for prefetching from a system memory address;

(b) copying said count from a general purpose register of the microprocessor to a prefetch count register;

(c) storing said address in a prefetch address register;

(d) prefetching a cache line specified by said prefetch address register into the cache;

(e) decrementing said prefetch count register;

(f) incrementing said prefetch address register;

(g) repeating said steps (d), (e), and (f) until said prefetch count register reaches a zero value; and

skipping step (d) if said address generates a hit in the cache.