Methods and apparatus for control of asynchronous cache

• US 6,832,300 B2
• Filed: 03/20/2002
• Issued: 12/14/2004
• Est. Priority Date: 03/20/2002
• Status: Expired due to Term

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Soltis, Donald C. Jr., Naffziger, Samuel David
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): PATEL, HETUL B
• Application Number:
  US10/103,204
• Publication Number:
  US 20030182507A1
• Time in Patent Office: 1,000 Days
• Field of Search: 711/118, 711/167, 711/169
• US Class Current: 711/169
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence

Abstract

A processing system includes a cache controller for managing requests for data from a cache memory by a processor. The cache controller includes an access queue that holds requests for data pending asynchronous retrieval of the requested data from the cache memory, and an exit queue that holds the requested data retrieved from the cache memory until released to the processor. This queuing arrangement allows data lines to be retrieved from cache memory without a pipeline, while latencies are minimized.

Claims

1. A processing system comprising a cache controller for managing requests for data from a cache memory by a processor, the cache controller comprising:

an access queue comprised of a plurality of access queue registers configured to hold requests for data pending asynchronous retrieval of the requested data from the cache memory;

an exit queue comprised of a plurality of exit queue registers configured to hold the retrieved requested data until released to the processor; and

a plurality of self-clocked state machines operating in one-to-one correspondence with pairs of the access and exit queue registers for the retrieving requested data from the cache memory asynchronously relative to a frequency domain of the cache controller.

2. The processing system of claim 1 wherein the retrieved data is loaded into the exit queue in an order determined by relative latencies in retrieving the data.

3. The processing system of claim 1 wherein the retrieved data is loaded into the exit queue in an order determined by the access queue.

4. The processing system of claim 1 wherein each of the exit queue registers is further configured to hold an address tag for identifying the corresponding access queue register.

5. The processing system of claim 1 further comprising a reactive synchronizer for synchronizing return of the requested data to a frequency domain of the exit queue.

6. The processing system of claim 1 wherein the cache controller is configured to hold a plurality of requests for data from the cache memory outstanding at one time.

7. A processing system comprising a plurality of processors and a cache memory allocated among the processors, at least one of the processors comprising a cache controller configured to control processor requests for retrieval of data from the cache memory, from which the requested data is retrieved asynchronously relative to a frequency domain of the requesting processor;

the cache controller comprising an access queue having a plurality of access registers in which a cache memory address of the requested data is placed and an exit queue having a plurality of data return registers in which the requested data is placed when retrieved from the cache memory; and

a plurality of self-clocked state machines operating in one-to-one correspondence with pairs of the access queue and data return registers for retrieving the requested data from the cache memory asynchronously relative to a frequency domain of the cache controller;

wherein the cache controller is further configured to release, to the processor, the retrieved data in the data return register corresponding to an access queue register holding a cache memory address of the retrieved data.

8. The processing system of claim 7 wherein the cache memory address of the requested data is placed in the access queue upon issuance of a request by the processor.

9. The processing system of claim 7 wherein data requests are transferred from the access queue to the cache memory in an order in which the requests are placed in the access queue.

10. The processing system of claim 7 wherein the processing system is fabricated on a single die.

11. The processing system of claim 7 wherein the access and exit queues are configured to return retrieved data in an order based on relative latencies in retrieving the data.

12. The processing system of claim 7 wherein the data return register corresponds to the access queue register based on an address tag returned with the requested data.

13. A method for performing data retrieval from a cache memory in a processing system wherein a processor issues requests for data from the cache memory, the method comprising the steps of:

providing an access queue having a plurality of access registers an exit queue having a plurality of data return registers and a plurality of self-clocked state machines operating in one-to-one correspondence with pairs of the access queue and data return registers;

asynchronously retrieving data requested from the cache memory, said step performed using a one of the plurality of self-clocked state machines;

returning the requested data to one of the data return registers clocked with the processor, said step performed using a reactive synchronizer; and

releasing the returned data to the processor from the one exit queue register.

14. The method of claim 13 wherein the step of releasing the returned data comprises releasing first to the processor a data line received pursuant to a last-issued data request to the cache memory.

15. The method of claim 13 wherein the step of releasing the returned data comprises releasing data lines to the processor in an order in which the data lines are requested by the processor.

16. The method of claim 13 further comprising the step of issuing data requests to the cache memory in order of receipt of the data requests from the processor, said step performed using the access queue.

17. The method of claim 13 wherein the step of releasing the returned data comprises releasing data lines to the processor in an order based on relative latencies in retrieving the data from the cache memory.