Apparatus and method for providing an external clock from a circuit in sleep mode in a processor-based system

• US 6,832,327 B1
• Filed: 10/02/2001
• Issued: 12/14/2004
• Est. Priority Date: 10/02/2001
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Quimby, Michael S., Magro, James R.
• Primary Examiner(s): Perveen, Rehana
• Application Number:
  US09/969,304
• Time in Patent Office: 1,169 Days
• Field of Search: 713/500, 713/320, 713/300, 327/407, 327/298, 714/731
• US Class Current: 713/500
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G11C 2207/16 Solid state audio
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor-based system such as a workstation or server, using a system clock provided through a phase-locked loop (PLL) to a clock gate and then to a clock tree, which distributes the core system clock to components in the processor-based system, including a host bridge circuit. The host bridge distributes control signals to a receiving device such as a memory module, which may use a continued clocking signal when the system enters a low-power mode. A feedback clock for the PLL is provided to the receiving devices during low-power mode to ensure continued clocking, when the clock gate output is low and the clock tree is thereby disabled. A skew compensation circuit coordinates clocking in the continued clock and the core system clock.

Claims

1. A clock circuit coupled to a core clock signal of a processor-based system, including:

a first subcircuit configured to selectively provide and inhibit passage of the core clock signal to a control circuit, and coupled to a receiving device configured to receive the core clock signal when it is passed by the first subcircuit; and

a second subcircuit coupled to receive a continued clock signal based upon the core clock circuit and to pass the continued clock signal to the receiving device even when the first subcircuit inhibits passage of the core clock circuit to the control circuit.

2. The clock circuit of claim 1, wherein:

the clock circuit is configured to receive a double-frequency clock signal derived from the core clock signal; and

the second subcircuit further includes a skew compensation circuit configured to reduce skew between the continued clock signal and the core clock signal as passed by the first subcircuit.

3. The clock circuit of claim 2, wherein the second subcircuit includes a delay circuit coupled to receive the double-frequency clock signal and configured to output a signal from the control circuit with timing coordinated with the continued clock signal passed by the first subcircuit.

4. The clock circuit of claim 1, wherein:

the receiving device includes a double-data rate memory module;

the control circuit includes a memory controller; and

the first subcircuit is configured to pass the continued clock signal as a differential clock signal to the double-data rate memory module to drive the memory module even when the memory controller does not receive the core clock signal.

5. A processor-based system configured to generate a system clock signal and having a microprocessor configured to execute instructions accessing a memory module, the system including:

a host bridge coupled to the memory module and configured to pass control signals to the memory module;

a phase-locked loop (PLL) circuit coupled to receive the system clock signal and to output a phase-locked core clock signal;

a clock tree circuit configured to distribute the core clock signal to the host bridge;

a first gate configured to receive the core clock signal, and to pass the core clock signal to the clock tree circuit when the system is in an active mode, and to inhibit passage of the core clock signal when the system is in a low-power mode; and

a clock bypass circuit, configured to distribute the core clock signal to the memory module whether the system is in the active mode or the low-power mode.

6. The system of claim 5, wherein the core clock signal distributed by the clock bypass clock circuit comprises a feedback clock signal of the PLL circuit.

7. The system of claim 5, further including:

a delay circuit coupled to receive the control signals from the host bridge and pass the received control signals to the memory module;

wherein the PLL circuit is further configured to generate a double-frequency (2×

) clock signal based upon the system clock signal, and to pass the 2×

clock signal to the delay circuit and to the bypass circuit, the delay circuit and bypass circuit being configured to coordinating timing of the respective signals passing through them with the 2×

clock signal.

8. The system of claim 7, wherein:

the bypass circuit includes a skew compensation circuit configured to be clocked by the 2×

clock.

9. The system of claim 8, wherein the skew compensation circuit includes at least one input gate configured to be clocked by a first edge of the 2×

clock, having as an input a feedback core clock signal from the PLL circuit, and having as output a synchronized feedback core clock signal substantially aligned with the first edge of the 2×

clock.

10. The system of claim 9, wherein the first edge of the 2×

clock is a falling edge, and the skew compensation circuit further includes;

a first output gate configured to be clocked by a rising edge of the 2×

clock, having the synchronized feedback core clock signal as an input, and having as output a further synchronized core clock signal; and

a second output gate configured to be clocked by the rising edge of the 2×

clock, having an inverted form of the synchronized feedback core clock signal as input, and having as output an inverted form of the further synchronized core clock signal;

wherein the further synchronized core clock signal and inverted further synchronized core clock signal are coupled to be provided as a differential clock signal to the memory module.

11. A method for substantially continuous clocking of a receiving device coupled to a processor-based system, including the steps of:

providing a core clock signal to a host bridge having as outputs control signals coupled to the receiving device when the system is in an active mode;

inhibiting passage of the core clock signal to the host bridge when the system is in a low-power mode; and

providing a bypass clock signal to the receiving device both when the system is in the active mode and when the system is in the low-power mode.

12. The method of claim 11, wherein the step of providing the core clock signal includes passing the core clock signal through a phase-locked loop (PLL) circuit.

13. The method of claim 12, further including the step of generating a double-frequency (2×

) clock signal by the PLL circuit, the 2×

clock signal being based upon and having substantially double a frequency of the core clock signal.

14. The method of claim 13, further including the step of deskewing the bypass clock signal relative to the core clock signal passed to the host bridge.

15. The method of claim 14, wherein the deskewing step includes the steps of:

clocking the bypass clock signal using a first edge of the 2×

clock signal to generate an aligned form of the bypass clock signal by; and

clocking the core clock signal passed to the host bridge using the first edge of the 2×

clock signal, to generate a form of the core clock signal substantially coordinated with the aligned form of the bypass clock signal.

16. The method of claim 15, wherein the first edge of the 2×

clock signal is a falling edge, and the step of clocking the bypass clock signal includes the steps of;

passing the bypass clock signal through at least one input gate clocked by the first edge of the 2×

clock signal;

passing the bypass clock signal as output from the input gate through a first output gate in a noninverted form, the first output gate being clocked by a rising edge of the 2×

clock signal;

generating an inverted form of the bypass clock after output from the input gate; and

passing the inverted form of the bypass clock signal through a second output gate, the second output gate being clocked by the rising edge of the 2×

clock signal.

17. The method of claim 16, further including the step of providing both the noninverted and inverted forms of the bypass clock signal to the receiving device as a differential clock signal.

18. The method of claim 11, wherein the receiving device includes a memory module, the method further including the step of providing the bypass clock signal to the memory module as a differential clock signal.

19. The method of claim 11, further including the step of substantially synchronizing at least one of the control signals with the bypass clock signal when the system is in the active mode.

20. The method of claim 11, further including the step of reducing skew between the bypass clock signal and the core clock control signals.

21. The method of claim 20, wherein the step of reducing skew is carried out at least in part by passing the bypass clock signal through a delay-matching circuit configured to match delay introduced to the core clock signal as it is passed to the host bridge.