System and method for obtaining hysteresis through body substrate control

• US 6,833,749 B2
• Filed: 12/09/2002
• Issued: 12/21/2004
• Est. Priority Date: 12/09/2002
• Status: Expired due to Fees

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Erstad, David Owen
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US10/314,708
• Publication Number:
  US 20040108874A1
• Time in Patent Office: 743 Days
• Field of Search: 327/108, 327/111, 327/112, 327/109, 327/534, 327/537, 327/170, 327/379, 327/389, 327/391, 327/427, 327/431, 327/434, 327/437, 327/205, 327/206, 327/581, 326/24, 326/27, 326/83
• US Class Current: 327/534
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A buffer circuit is used to provide hysteresis, which can reduce the negative effects of noise in digital circuits. Reducing the number of transistors in the buffer circuit reduces the amount of space the circuit occupies and reduces power consumption. By connecting a voltage-coupling element between the body of a transistor in a first inverter and an output of a second inverter, the voltage-coupling element can control the hysteresis of the buffer circuit.

Claims

1. A buffer circuit, comprising in combination:

a first stage element that receives at least one input signal and generates at least one intermediate signal having hysteresis characteristics;

a second stage element receiving the at least one intermediate signal from the first stage element, wherein the second stage element generates an output signal at an output terminal based on the at least one intermediate signal; and

at least one coupling element connected to the output terminal of the second stage element and at least one body terminal of the first stage element, wherein the at least one coupling element comprises at least one resistor, wherein the at least one resistor provides a conduction path capable of providing a bias voltage from the output signal to the at least one body terminal of the first stage element, thereby controlling the hysteresis characteristics of the at least one intermediate signal.

2. The buffer circuit of claim 1, wherein the first stage element includes a first logic circuit, and the second stage element includes a second logic circuit.

3. The buffer circuit of claim 2, wherein the first logic circuit comprises a first inverter, and the second logic circuit comprises a second inverter, wherein the first inverter is coupled in series to the second inverter.

4. The buffer circuit of claim 3, wherein the first inverter includes a first pair of p-channel and n-channel transistors, and wherein an output terminal of the second inverter is connected to a body terminal of the p-channel transistor via the at least one resistor.

5. The buffer circuit of claim 3, wherein the first inverter includes a first pair of p-channel and n-channel transistors, and wherein an output terminal of the second inverter is connected to a body terminal of the n-channel transistor via the at least one resistor.

6. The buffer circuit of claim 3, wherein the first inverter includes a first pair of p-channel and n-channel transistors, and the at least one resistor comprises a first resistor and a second resistor, the first resistor coupling an output terminal of the second inverter to body terminal of the p-channel transistor, and the second resistor coupling the output terminal of the second inverter to a body terminal of the n-channel transistor.

7. The buffer circuit of claim 2, wherein the first logic circuit provides a logic function selected from the group consisting of inverter, NOR, and NAND.

8. The buffer circuit of claim 2, wherein the second logic circuit provides a logic function selected from the group consisting of inverter, NOR, and NAND.

9. A buffer circuit, comprising in combination:

a first inverter that receives an input signal and generates a first output signal, wherein the first output signal is an inverted input signal having hysteresis characteristics, and wherein the first inverter comprises a first pair of n-channel and p-channel transistors for receiving the input signal;

a second inverter that receives the first output signal from the first inverter and generates a second output signal, wherein the second output signal is an inverted first output signal, wherein the second inverter comprises a second pair of n-channel and p-channel transistors for receiving the first output signal from the first inverter; and

at least one coupling element coupled to the second output signal of the second inverter, wherein the at least one coupling element comprises at least one resistor, wherein the at least one resistor provides a conduction path capable of providing a bias voltage from the second output signal to at least one body terminal of the first pair of n-channel and p-channel transistors.

10. The buffer circuit of claim 9, wherein the at least one resistor is coupled between the second output signal and the n-channel transistor of the first inverter, thereby providing bias to the n-channel transistor and controlling the hysteresis characteristics of the first output signal.

11. The buffer circuit of claim 9, wherein the at least one resistor is coupled between the second output signal and the p-channel transistor of the first inverter, thereby providing bias to the p-channel transistor and controlling the hysteresis characteristics of the first output signal.

12. A method for controlling hysteresis in a buffer circuit, comprising connecting at least one coupling element between a body of a transistor in a first inverter and an output of a second inverter, wherein the at least one coupling element comprises at least one resistor, whereby the at least one resistor provides a conduction path capable of providing a bias voltage from the output of the second inverter to the body of the transistor in the first inverter.