System and method for enabling multiple signed independent data elements per register
First Claim
1. A computer system, comprising:
- a processor, the processor using logic for undertaking method acts to enable the simultaneous processing of multiple multi-bit data elements in a single register, the method acts undertaken by the logic including;
establishing at least first and second signed, multi-bit data elements in at least a first register;
simultaneously processing the elements, wherein the first element is provided from a first data set and the second element is provided from a second data set different than the first;
allocating a respective precision in a register for each data element to be processed in the register during a single cycle such that a maximum negative number that can be represented by a data element is one larger than the maximum negative number that can be represented in the respective precision.
1 Assignment
0 Petitions
Accused Products
Abstract
A system and method for data processing includes packing multiple signed data elements per register into a processor'"'"'s registers using the rules set forth herein, and simultaneously operating on the elements in a register in a single cycle using the same operand. The elements can be independent of each other, and the sizes of the elements in a register can differ from each other. Moreover, a relatively large element can be split across multiple registers. In an exemplary application, a data stream representing two images can be simultaneously processed using the same number of registers as have been required to process a single image. Or, a single image can be processed approaching N-times faster, where N is the number of elements per register. In any case, the present invention results in a significant increase in processing efficiency.
44 Citations
46 Claims
-
1. A computer system, comprising:
-
a processor, the processor using logic for undertaking method acts to enable the simultaneous processing of multiple multi-bit data elements in a single register, the method acts undertaken by the logic including;
establishing at least first and second signed, multi-bit data elements in at least a first register;
simultaneously processing the elements, wherein the first element is provided from a first data set and the second element is provided from a second data set different than the first;
allocating a respective precision in a register for each data element to be processed in the register during a single cycle such that a maximum negative number that can be represented by a data element is one larger than the maximum negative number that can be represented in the respective precision. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14)
determining whether a data element is contained around zero.
-
-
7. The processor of claim 1, wherein the method acts undertaken by the logic include:
-
preserving, in a first register, a sign bit for a data element packed in a second register;
zeroing at least one least significant bit to be shifted out of the data element pursuant to undertaking shift-right arithmetic;
performing an arithmetic shift right; and
restoring sign bits to the data element.
-
-
8. The processor of claim 7, wherein the method acts undertaken by the logic include:
if subsequent operations are to be personnel, subtracting the sign bits to repack the register.
-
9. The processor of claim 1, wherein the method acts undertaken by the logic include:
undertaking at least one equality confirmation on at least two data elements in a single register during a single processing cycle.
-
10. The processor of claim 1, wherein the method acts undertaken by the logic include:
undertaking at least one arithmetic compare on at least one comparison element in a single register containing at least two elements in a single processing cycle.
-
11. The processor of claim 10, wherein the arithmetic compare includes using the sign bit of a right-adjacent element to the comparison element.
-
13. The processor of claim 1, wherein the method acts undertaken by the logic include:
-
executing a program by;
packing multiple data elements into at least one single register;
simultaneously operating on all data elements in the single register; and
passing the data elements on for further processing, storage, or output after the operating act.
-
-
14. The processor of claim 13, wherein the method acts undertaken by the logic include:
for at least first and second data elements in a single register that are to be independent of each other, adding a sign bit in the first element to a cast significant bit in the second element.
-
12. A computer system, comprising:
-
a processor, the processor using logic for undertaking method acts to enable the simultaneous processing of multiple multi-bit data elements in a single register, the method acts undertaken by the logic including;
establishing at least first and second signed, multi-bit data elements in at least a first register;
simultaneously processing the elements;
determining a net number of bits required for any multiplicative constants to achieve a desired precision;
using the net number of bits and multiplicative constant, determining a net number of bits of precision; and
allocating space in the register in accordance with the using act.
-
-
15. A computer system comprising:
-
a processor, the processor using logic for undertaking method acts to enable the simultaneous processing of multiple multi-bit data elements in a single register, the method acts undertaken by the logic including;
establishing at least first and second signed, multi-bit data elements in at least a first register;
simultaneously processing the elements, wherein the first element is provided from a first data set and the second element is provided from a second data set different than the first;
splitting, into two or more sub-elements, at least one relatively large data element and packing the sub-elements into separate respective registers; and
recombining the sub-elements after processing.
-
-
16. A computer system, comprising:
-
a processor, the processor using logic for undertaking method acts to enable the simultaneous processing of multiple multi-bit data elements in a single register, the method acts undertaken by the logic including;
establishing at least first and second signed, multi-bit data elements in at least a first register;
simultaneously processing the elements; and
determining a precision bound for a data element based on [−
2N−
1+1] to [2N−
1−
1], wherein N is the number of bits in the data element.
-
-
17. A computer program device comprising:
-
a computer program storage device readable by a digital processing apparatus; and
a program on the program storage device and including instructions executable by the digital processing apparatus for performing method acts for processing multi-bit, signed data elements, the program comprising;
computer readable code means for packing at least first and second data elements into a single register;
computer readable code means for processing the elements simultaneously;
computer readable code means for determining a net number of bits required for any multiplicative constants to achieve a desired precision;
computer readable code means for using the net number of bits and multiplicative constant to determine a net number of bits of precision; and
computer readable code means for allocating space in the register in accordance with the using act. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
computer readable code means for allocating a respective precision in a register for each data element to be processed in the register during a single cycle such that the maximum negative number that can be represented by a data element is one larger than the maximum negative number that can be represented in the respective precision.
-
-
19. The computer program device of claim 17, further comprising:
-
computer readable code means for executing a program by;
packing multiple data elements into at least one single register according to the net number of bits of precision;
simultaneously operating on all data elements in the single register; and
passing the data elements on for further processing, storage, or output after the operating act.
-
-
20. The computer program device of claim 19, further comprising:
computer readable code means for, for at least first and second data elements in a single register that are to be independent of each other, adding a sign bit in the first element to a least significant bit in the second element.
-
21. The computer program device of claim 19, further comprising:
-
computer readable code means for splitting, into two or more sub-elements, at least one relatively large data element and packing the sub-elements into separate respective registers;
computer readable code means for recombining the sub-elements after processing.
-
-
22. The computer program device of claim 21, further comprising:
computer readable code means for determining whether a data element is contained around zero.
-
23. The computer program device of claim 22, further comprising:
-
computer readable code means for preserving, in a first register, a sign bit for a data element packed in a second register;
computer readable code means for zeroing at least one least significant bit to be shifted out of the data element pursuant to undertaking shift-right arithmetic;
computer readable code means for performing an arithmetic shift right; and
computer readable code means for restoring the sign bits and guard bits to the data element.
-
-
24. The computer program device of claim 23, further comprising:
computer readable code means for undertaking at least one equality confirmation on at least two data elements in a single register during a single processing cycle.
-
25. A method, comprising:
-
determining first and second precisions to be allocated in a single register to hold respective first and second signed data elements;
packing the elements into the register;
operating on the elements;
determining third and fourth precisions to be allocated in the single register to hold respective third and fourth signed data elements, at least one of;
the first and third precision being different from each other, and the second and fourth precisions being different from each other;
packing the third and fourth elements into the register; and
operating on the third and fourth elements. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
allocating a respective precision in a register for each data element to be processed in the register during a single cycle such that the maximum negative number that can be represented by a data element is one larger than the maximum negative number that can be represented in the respective precision.
-
-
36. The method of claim 35, further comprising:
-
determining a net number of bits required for any multiplicative constants to achieve a desired precision;
using the net number of bits and multiplicative constant, determining a net number of bits of precision; and
allocating space in the register in accordance with the using act.
-
-
37. The method of claim 36, further comprising:
-
executing a program by;
packing multiple data elements into at least one single register according to the net number of bits of precision;
simultaneously operating on all data elements in the single register; and
passing the data elements on for further processing, storage, or output after the operating act.
-
-
38. The method of claim 37, further comprising;
for at least first and second data elements in a single register that are to be independent of each other, adding a sign bit in the first element to a least significant bit in the second element.
-
39. The method of claim 37, further comprising:
splitting, into two or more sub-elements, at least one relatively large data element and packing the sub-elements into separate respective registers; and
recombining the sub-elements after processing.
-
40. The method of claim 35, further comprising determining a precision bound for a data element based on [−
- 2N−
1+1] to [2N−
1−
1], wherein N is the number of bits in the data element.
- 2N−
-
41. The method of claim 25, further comprising:
determining whether a data element is contained around zero.
-
42. The method of claim 25, further comprising:
-
preserving, in a first register, sign bits for a data element packed in a second register;
zeroing at least one least significant bit to be shifted out of the data element pursuant to undertaking shift-right arithmetic; and
restoring the sign bits to the data element.
-
-
43. The method of claim 25, further comprising:
undertaking at least one equality confirmation on at least two data elements in a single register during a single processing cycle.
-
44. A computer system, comprising:
-
a processor, the processor using logic for undertaking method acts to enable the simultaneous processing of multiple multi-bit data elements in a single register, the method acts undertaken by the logic including;
establishing at least first and second signed, multi-bit data elements in at least a first register;
simultaneously processing the elements;
for at least first and second data elements in a single register, masking sign bits in the first and second elements;
adding the sign bits back in to the register; and
discarding a value in a position of the sign bits in each element.
-
-
45. A computer program device comprising:
-
a computer program storage device readable by a digital processing apparatus; and
a program on the program storage device and including instructions executable by the digital processing apparatus for performing method acts for processing multi-bit, signed data elements, the program comprising;
computer readable code means for packing at least first and second data elements into a single register;
computer readable code means for processing the elements simultaneously;
computer readable code means for, for at least first and second data elements in a single register that are to be independent of each other, masking sign bits in the first and second elements;
computer readable code means for adding the sign bits back in to the register; and
computer readable code means for discarding a position of the sign bits in each element, with the possible exception of the sign bit for a left-most element in the register.
-
-
46. A method, comprising:
-
determining first and second precisions to be allocated in a single register to hold respective first and second signed data elements;
packing the elements into the register;
operating on the elements;
determining third and fourth precisions to be allocated in the single register to bold respective third and fourth signed data elements, at least one of;
the first and third precision being different from each other, and the second and fourth precisions being different from each other;
packing the third and fourth elements into the register;
operating on the third and fourth elements;
for at least first and second data elements in a single register that are to be independent of each other masking sign bits in the first and second elements;
adding the sign bits back in to the register; and
discarding a position of the sign bits in each element.
-
Specification