Methods and apparatus for upgrading firmware in an embedded system

• US 6,834,384 B2
• Filed: 03/14/2001
• Issued: 12/21/2004
• Est. Priority Date: 03/14/2001
• Status: Expired due to Fees

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Inventors: Fiorella, Daniel Charles III, McGregor, Marlin F. Jr., Gebhardt, Ronald L. Jr.
• Primary Examiner(s): Nguyen-Ba, Antony
• Assistant Examiner(s): Vo, Ted T.
• Application Number:
  US09/808,370
• Publication Number:
  US 20020170050A1
• Time in Patent Office: 1,378 Days
• Field of Search: 717/168-178, 717/122, 711/100-111, 711/1-6, 711/128-130, 711/152-159, 711/170-173, 711/205-210, 711/270, 712/2-9, 712/13-15, 712/36-40, 712/204, 712/233, 710/260-269, 714/6-9, 714/34, 714/35, 714/41, 714/42, 714/758, 714/759, 714/765-769
• US Class Current: 717/169
• CPC Class Codes: G06F 8/656 while running

Abstract

The present invention provides methods and apparatus for upgrading firmware in an embedded system, without impacting the system. More specifically, the present invention enables an embedded system to be upgraded without any system downtime, by providing two application areas in non-volatile programmable read only memory. A processor can boot up and run from either application area. A fixed vector table is provided, which, in cooperation with a software vector table, enables the processor to maintain proper interrupt vector addresses while being able to run from either application area. Upgraded firmware can be loaded into one application area while the system is running from the other application area. Resetting the processor allows the system to run the upgraded version of firmware.

Claims

1. A method for upgrading firmware in an embedded system, comprising the steps of:

providing a processor;

providing a non-volatile programmable read only memory device having a fixed vector table, a boot area for storing boot code, a first application area for storing firmware, and a second application area for storing firmware;

providing a random access memory device (RAM) having a software vector table and a RAM application area;

programming the fixed vector table with a reset vector address and interrupt vector addresses, said reset vector address pointing to the boot code in said boot area and said interrupt vector addresses pointing to corresponding interrupt vector addresses in the software vector table;

loading an upgraded version of firmware into one of the first application area or the second application area;

resetting the processor to run the upgraded version of firmware; and

filling the software vector table with proper corresponding interrupt vector addresses for the interrupt vectors contained in the fixed vector table as determined by the upgraded version of firmware;

wherein;

in the event an interrupt is generated, the processor obtains a next instruction from one of the interrupt vector addresses of the fixed vector table in accordance with said interrupt;

said next instruction points to a corresponding location in the software vector table; and

said corresponding location in the software vector table points to a corresponding location in one of said first or second application areas.

2. A method in accordance with claim 1, wherein the non-volatile programmable read only memory device comprises a flash electrically erasable programmable read only memory device (FLASH).

3. A method in accordance with claim 1, wherein a prior version of firmware is running from one application area while the upgraded version of firmware is being loaded into the other application area.

4. A method in accordance with claim 1, further comprising:

providing an erasable programmable memory device (EPROM) which is used to determine which application area will be accessed after the resetting step.

5. A method in accordance with claim 1, further comprising:

loading the RAM application area with data from the application area having the upgraded version of firmware.

6. A method in accordance with claim 1, wherein:

the first application area contains a first version of firmware; and

the second application area contains a second version of firmware.

7. A method in accordance with claim 1, wherein said processor, said non-volatile programmable read only memory device, and said RAM are all provided in the form of a single integrated circuit.

8. An upgradable embedded system apparatus, comprising:

a processor;

a non-volatile programmable read only memory device having a fixed vector table, a boot area for storing boot code, a first application area for storing firmware, and a second application area for storing firmware; and

a random access memory device (RAM) having a software vector table and a RAM application area;

wherein;

the fixed vector table is programmed with a reset vector address and interrupt vector addresses, said reset vector address pointing to the boot code in said boot area and said interrupt vector addresses pointing to corresponding interrupt vector addresses in the software vector table;

an upgraded version of firmware is loaded into one of the first application area or the second application area;

the processor is reset to run the upgraded version of firmware;

the software vector table is filled with proper corresponding interrupt vector addresses for the interrupt vectors contained in the fixed vector table as determined by the upgraded version of firmware;

in the event an interrupt is generated, the processor obtains a next instruction from one of the interrupt vector addresses of the fixed vector table in accordance with said interrupt;

said next instruction points to a corresponding location in the software vector table; and

said corresponding location in the software vector table points to a corresponding location in one of said first or second application areas.

9. Apparatus in accordance with claim 8, wherein the non-volatile programmable read only memory device comprises a flash electrically erasable programmable read only memory device (FLASH).

10. Apparatus in accordance with claim 8, wherein a prior version of firmware is running from the one application area while the upgraded version of firmware is being loaded into the other application area.

11. Apparatus in accordance with claim 8, further comprising:

an erasable programmable memory device (EPROM) which is used to determine which application area will be accessed after the resetting step.

12. Apparatus in accordance with claim 8, wherein:

the RAM application area is loaded with data from the application area having the upgraded version of firmware.

13. Apparatus in accordance with claim 8, wherein:

the first application area contains a first version of firmware; and

the second application area contains a second version of firmware.

14. Apparatus in accordance with claim 8, wherein said processor, said non-volatile programmable read only memory device, and said RAM are all provided in the form of a single integrated circuit.