Semiconductor package

• US 6,835,597 B2
• Filed: 06/26/2003
• Issued: 12/28/2004
• Est. Priority Date: 04/27/2001
• Status: Expired due to Term

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Murayama, Kei
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/603,812
• Publication Number:
  US 20040004293A1
• Time in Patent Office: 551 Days
• Field of Search: 438/106, 438/108, 438/128-129
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/09663 Divided layout, i.e. conductors divided in two or more parts
• CPC Class Codes: H05K 2201/09772 Conductors directly under a component but not electrically connected to the component
• CPC Class Codes: H05K 2201/10318 Surface mounted metallic pins
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.

Claims

1. A process of producing a semiconductor package comprising:

forming a plurality of pad segments forming each of plural pads to which each external connection terminal is bonded while opening up spaces between the pad segments sufficient for passing interconnections therethrough when forming an interconnection layer including interconnection patterns and the pads on an insulating substrate or insulating layer;

forming a protective layer covering said interconnection layer other than at portions of pads formed by said plurality of pad segments and said insulating substrate or Insulating layer; and

bonding one external connection terminal to each pad formed by said plurality of pad segments exposed from said protective layer.

2. A process of producing a semiconductor module as set forth in claim 1, further comprising:

forming a protective film; and

forming a plating film for improving adhesion when bonding the external connection terminals to the pad segments exposed from said protective film.

3. A process of producing a semiconductor package comprising:

forming a plurality of pads on an insulating substrate, each of the plurality of pads having plural pad segments separated by spaces therebetween; and

forming interconnection layers on the insulating substrate, each interconnection layer connecting with at least one pad segment of each of the plurality of pads to connect the at least one pad segment of each pad with other interconnection layers within the semiconductor package while the pad segments not connected with the interconnection layers to be connected externally of the semiconductor package.