Method of manufacturing semiconductor device having gate electrode with expanded upper portion

• US 6,835,610 B2
• Filed: 06/03/2003
• Issued: 12/28/2004
• Est. Priority Date: 09/04/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Oda, Hidekazu, Ohta, Kazunobu, Sayama, Hirokazu, Sugihara, Kouhei
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): Le, Thao P.
• Application Number:
  US10/452,309
• Publication Number:
  US 20040043549A1
• Time in Patent Office: 574 Days
• Field of Search: 438/199, 438/197
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28044 the conductor comprising at least another non-silicon conductive layer
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

A method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a polysilicon layer on the gate insulating film, implanting ions into the polysilicon layer, patterning the polysilicon layer to form a gate electrode, annealing the gate electrode, and siliciding an upper portion of the gate electrode to form a silicide layer that has a lower portion facing the gate electrode and an upper portion opposite to the lower portion, the upper portion of the silicide layer being wider than the lower portion. A total dose of ions implanted during the step of implanting is 6×10¹⁵/cm² or larger.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a semiconductor substrate and forming a polysilicon layer on said gate insulating film;

implanting ions into said polysilicon layer;

patterning said polysilicon layer to form a gate electrode;

annealing said gate electrode; and

siliciding an upper portion of said gate electrode to form a silicide layer that has a lower portion facing said gate electrode and an upper portion opposite to said lower portion, said upper portion of said silicide layer being wider than said lower portion,

wherein a total dose of said ions to be implanted in said implanting is 6×

10¹⁵/cm² or larger.

2. The method of manufacturing a semiconductor device according to claim 1,

wherein said ions to be implanted in said implanting include an ion having a mass number of 70 or larger.

3. The method of manufacturing a semiconductor device according to claim 1,

wherein said ions to be implanted in said implanting include an electrically inactive ion.

4. The method of manufacturing a semiconductor device according to claim 1,

wherein said implanting includes ion implantation using a metal as an ion species.

5. The method of manufacturing a semiconductor device according to claim 1,

wherein said implanting includes the forming a source/drain region in said semiconductor substrate by ion implantation using said gate electrode as a mask, and said forming a source/drain region being performed after said patterning.

6. The method of manufacturing a semiconductor device according to claim 5,

wherein said implanting includes implanting ions into an entire surface of said polysilicon layer, said implanting ions into an entire surface being performed before said patterning.

7. The method of manufacturing a semiconductor device according to claim 5, further comprising:

forming a sidewall on a side face of said gate electrode,

wherein said forming a source/drain region includes;

carrying out a first ion implantation using said gate electrode as a mask, before said forming a sidewall; and

carrying out a second ion implantation using said gate electrode and said sidewall as a mask, after said forming a sidewall.

8. The method of manufacturing a semiconductor device according to claim 7,

wherein said implanting further includes carrying out a third ion implantation using a metal as an ion species, on said gate electrode and said sidewall, said carrying out a third ion implantation being performed after said forming a sidewall, and

said method further comprising:

etching a surface of said sidewall after said carrying out a third ion implantation.

9. The method of manufacturing a semiconductor device according to claim 5, further comprising:

forming a first sidewall on a side face of said gate electrode;

removing said first sidewall; and

forming a second sidewall on said side face of said gate electrode after said removing said first sidewall,

wherein said implanting further includes carrying out a first ion implantation using a metal as an ion species, on said gate electrode and said first sidewall, said carrying out a first ion implantation being performed between said forming a first sidewall and said removing said first sidewall.

10. The method of manufacturing a semiconductor device according to claim 9,

wherein said forming a source/drain region includes

carrying out a second ion implantation using said gate electrode and said first sidewall as a mask, between said forming a first sidewall and said removing said first sidewall;

and

carrying out a third ion implantation using said gate electrode as a mask, between said removing said first sidewall and said forming a second sidewall and after said annealing.

11. A method of manufacturing a semiconductor device including a p-channel MOS transistor and an n-channel MOS transistor, comprising:

forming a gate insulating film on a semiconductor substrate, and forming a polysilicon layer on said gate insulating film;

implanting phosphorus ions into an entire surface of said polysilicon layer except a region where said p-channel MOS transistor is to be formed;

patterning said polysilicon layer to form respective gate electrodes of said p-channel MOS transistor and said n-channel MOS transistor, said patterning being performed after said implanting;

forming a source/drain region of said n-channel MOS transistor in said semiconductor substrate by ion implantation using said gate electrode of said n-channel MOS transistor as a mask;

forming a source/drain region of said p-channel MOS transistor in said semiconductor substrate by another ion implantation using said gate electrode of said p-channel MOS transistor as a mask;

annealing said respective gate electrodes of said p-channel MOS transistor and said n-channel MOS transistor; and

siliciding an upper portion of each of said respective gate electrodes of said p-channel MOS transistor and said n-channel MOS transistor to form corresponding silicide layers, each suicide layer having (i) a lower portion facing a corresponding gate electrode and (ii) an upper portion opposite to said lower portion, at least one suicide layer having an upper portion wider than a corresponding lower portion,

wherein a total dose of ions implanted in said implanting and forming a source/drain region is 6×

10¹⁵/cm² or larger.