Method of forming a novel composite insulator spacer

• US 6,835,640 B2
• Filed: 12/06/2002
• Issued: 12/28/2004
• Est. Priority Date: 12/06/2002
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Hsiang-Fan, Lo, Chi-Hsin
• Primary Examiner(s): FOLEY, SHANON A
• Assistant Examiner(s): Luu, Chuong Anh
• Application Number:
  US10/313,500
• Publication Number:
  US 20040110363A1
• Time in Patent Office: 753 Days
• Field of Search: 438/446, 438/448, 438/696, 438/303, 438/595, 438/230, 438/231, 438/232, 438/706, 438/738, 438/304, 438/305, 438/306, 438/307, 438/267, 438/366
• US Class Current: 438/595
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A method of defining composite insulator spacers on the sides of conductive gate structures, with reduced risk of semiconductor damage at end point of the composite insulator spacer definition procedure, has been developed. The method features initial deposition of a thin underlying, silicon rich, undoped silica glass (USG), layer, comprised with a refractive index greater than 1.55. After deposition of a TEOS silicon oxide layer a first phase of an anisotropic RIE procedure, using a CF₄/CHF₃ etch chemistry, is used to selectively define a silicon oxide spacer component, with the first phase of the etch procedure terminating on the underlying silicon rich, USG layer. A second phase of the anisotropic RIE procedure is then employed using C₄F₈/CO/Ar as an etchant, selectively defining the underlying silicon rich, USG spacer component of the composite insulator spacer, with the second phase of the anisotropic RIE procedure selectively terminating at the surface of the semiconductor substrate, thus reducing the risk of substrate damage.

Claims

1. A method of forming composite insulator spacers on the sides of conductive gate structures, on a semiconductor substrate, comprising the steps of:

growing a gate insulator layer on said semiconductor substrate;

forming conductive gate structures on said gate insulator layer;

depositing a first insulator layer;

depositing a second insulator layer;

performing a first phase of an anisotropic dry etch procedure to form second insulator spacer components on said first insulator layer, with said first phase of said anisotropic dry etching procedure selectively terminating on said first insulator layer; and

performing a second phase of said anisotropic dry etch procedure wherein the etch rate ratio of said first insulator layer to said second insulator layer is between about 1.5 to 1, to 20 to 1, and the etch rate ratio of said first insulator layer to said semiconductor substrate is between about 3 to 1, to 100 to 1, to form first insulator spacer components, resulting in definition of said composite insulator spacers located on sides of said conductive gate structure with said composite insulator spacers comprised of said second insulator spacer components overlying said first insulator spacer components.

2. The method of claim 1, wherein said composite insulator spacers are formed on conductive gate structures of embedded dynamic random access memory (EDRAM), devices.

3. The method of claim 1, wherein said gate insulator layer is a silicon dioxide layer.

4. The method of claim 1, wherein said conductive gate structures are polysilicon gate structures.

5. The method of claim 1, wherein said first insulator layer is an undoped silicate glass(USG), layer, such as silicon oxide, obtained via LPCVD or PECVD procedures using silane or disilane, and nitrous oxide as reactants.

6. The method of claim 1, wherein said first insulator layer is a USG layer, such as a silicon rich, silicon oxide layer, featuring a refractive index between about 1.55 to 1.90.

7. The method of claim 1, wherein said second insulator layer is a silicon oxide layer, obtained via LPCVD or PECVD procedures, using TEOS as a source.

8. The method of claim 1, wherein said first phase of said anisotropic dry etch procedure is an anisotropic RIE procedure, performed using an etch ambient comprised of CF₄/CHF₃.

9. The method of claim 1, wherein said first phase of said anisotropic dry etch procedure features an etch rate ratio of said second insulator layer to said first insulator layer, of between about 1.5 to 1, to 10 to 1.

10. The method of claim 1, wherein said second phase of said anisotropic dry etch procedure is an anisotropic RIE procedure, performed using an etch ambient comprised of C₄F₈/CO/Ar.

11. A method of forming composite insulator spacers on the sides of polysilicon gate structures, on a semiconductor substrate, featuring a selective two phase anisotropic reactive ion etch procedure, comprising the steps of:

growing a silicon dioxide gate insulator layer on said semiconductor substrate;

forming said polysilicon gate structures on said silicon dioxide gate insulator layer;

depositing a silicon rich, undoped silica glass (USG), layer;

depositing a silicon oxide layer;

performing a first phase of said two phase anisotropic RIE procedure to form silicon oxide spacer components on said silicon rich, USG layer, with said first phase of said anisotropic RIE procedure selectively terminating on the top surface of said silicon rich, USG layer; and

performing a second phase of said two phase anisotropic RIE procedure forming silicon rich, USG spacer components, and resulting in definition of said composite insulator spacers on sides of said conductive gate structure with each composite insulator spacer comprised of a silicon oxide spacer component overlying a silicon rich, USG spacer component, with said second phase of said anisotropic RIE procedure selectively terminating on top surface of said semiconductor substrate located in a space between said polysilicon gate structures.

12. The method of claim 11, wherein said composite insulator spacers are used as features of embedded dynamic random access memory (EDRAM), devices.

13. The method of claim 11, wherein said silicon dioxide gate insulator layer is obtained via a thermal oxidation procedure, performed in an oxygen-steam ambient.

14. The method of claim 11, wherein said silicon rich, USG layer, is a silicon oxide layer, obtained via LPCVD or PECVD procedures using silane or disilane, and nitrous oxide as reactants.

15. The method of claim 11, wherein the refractive index of said silicon doped, USG layer is between about 1.55 to 1.90.

16. The method of claim 11, wherein said silicon oxide layer is obtained via LPCVD or PECVD procedures using TEOS as a source.

17. The method of claim 11, wherein said first phase of said two phase anisotropic RIE procedure is performed using CF₄/CHF₃ as an etchant.

18. The method of claim 11, wherein said first phase of said two phase anisotropic RIE procedure is performed featuring an etch rate ratio of said silicon oxide layer to said silicon rich, USG layer, of between about 1.5 to 1, to 10 to 1.

19. The method of claim 11, wherein said second phase of said two phase anisotropic RIE procedure is performed using C₄F₈/CO/Ar as an etchant.

20. The method of claim 11, wherein the etch rate ratio of said silicon rich USG layer to said semiconductor substrate, during said second phase of said two phase anisotropic RIE procedure using C₄F₈/CO/Ar as an etchant, is between about 3 to 1, to 100 to 1.

21. The method of claim 11, wherein the etch rate ratio of said silicon rich USG layer to said silicon oxide, during said second phase of said two phase anisotropic RIE procedure using C₄F₈/CO/Ar as an etchant, is between about 1.5 to 1, to 20 to 1.