ESD protection structure

• US 6,835,985 B2
• Filed: 12/09/2000
• Issued: 12/28/2004
• Est. Priority Date: 12/07/2000
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Cai, Jun, Song, Jun, Lo, Keng Foo, Hua, Guang Ping
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US09/733,836
• Publication Number:
  US 20020072178A1
• Time in Patent Office: 1,480 Days
• Field of Search: 257/355-363, 257/396, 257/397, 257/510-515, 438/221, 438/315, 438/361
• US Class Current: 257/356
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Claims

1. An electrostatic discharge protection structure comprising:

a semiconductor substrate, the semiconductor substrate having source and drain diffusion regions, the semiconductor substrate having respective source and drain wells under the source and drain diffusion regions;

a shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate to separate the source and drain diffusion regions and a portion of the source and drain wells; and

source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extending through the shallow trench isolation to contact the source and drain diffusion regions.

2. The electrostatic discharge protection structure as claimed in claim 1 wherein:

the source and drain wells are of a first conductivity type; and

including;

a source and a drain implant of a second conductivity type individually bridging the source and drain wells to the semiconductor substrate.

3. The electrostatic discharge protection structure as claimed in claim 1 wherein:

the source and drain diffusion regions have proximate and distal edges;

the shallow trench isolation has source and drain contact openings provided therein between the respective proximate and distal edges of the source and drain diffusion regions and open thereto; and

the source and drain contact structures respectively extend through the source and drain contact openings to respectively contact the source and drain diffusion regions.

4. The electrostatic discharge protection structure as claimed in claim 1 wherein:

the source and the drain wells are spaced proximate each other whereby the minimum value for efficient bipolar turn-on time is achieved.

5. An electrostatic discharge protection transistor comprising:

a semiconductor p-substrate, the semiconductor p-substrate having n+ source and n+ drain diffusion regions, the semiconductor p-substrate having respective source and drain n-wells under the n+ source and n+ drain diffusion regions;

a shallow trench isolation formed over the semiconductor p-substrate and into the semiconductor p-substrate to separate the n+ source and n+ drain diffusion regions and portions of the source and drain n-wells; and

source and drain contact structures respectively formed on the shallow trench isolation over the n+ source and n+ drain diffusion regions and extending through the shallow trench isolation to contact the n+ source and n+ drain diffusion regions.

6. The electrostatic discharge protection transistor as claimed in claim 5 including:

a p−

source and a p−

drain implant individually bridging the source and drain n-wells to the semiconductor p-substrate.

7. The electrostatic discharge protection transistor as claimed in claim 5 wherein:

the n+ source and n+ drain diffusion regions have proximate and distal edges;

the shallow trench isolation has source and drain contact openings provided therein between the proximate and distal edges of the n+ source and n+ drain diffusion regions and open thereto; and

the source and drain contact structures respectively extend through the source and drain contact openings to respectively contact the n+ source and n+ drain diffusion regions.

8. The electrostatic discharge protection transistor as claimed in claim 5 wherein:

the source and the drain n-wells are spaced apart by the shallow trench isolation a portion of the depths thereof from a surface of the semiconductor p-substrate but proximate each other whereby the minimum value for efficient bipolar turn-on time is achieved and the snapback breakdown occurs distally from the surface of the semiconductor p-substrate.