Bidirectional shallow trench superjunction device with resurf region

• US 6,835,993 B2
• Filed: 08/26/2003
• Issued: 12/28/2004
• Est. Priority Date: 08/27/2002
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kinzer, Daniel M., Sridevan, Srikant
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US10/649,929
• Publication Number:
  US 20040065934A1
• Time in Patent Office: 490 Days
• Field of Search: 257/330, 257/492
• US Class Current: 257/492
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0852 of DMOS transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A lateral conduction superjunction device has bidirectional conduction characteristics. In a first embodiment, spaced vertical trenches in a P substrate are lined with N diffusions. A central MOSgate structure is disposed centrally in the parallel trenches and source and drain electrodes are at the opposite respective ends of the trenches. In a second embodiment, flat layers of alternately opposite conductivity types have source and drain regions at their opposite ends. A trench MOSgate is disposed between the source region at one end of the layers to enable bidirectional currant flow through the stocked layers.

Claims

1. A bidirectional conduction superjunction device comprising a silicon substrate having a first and second laterally spaced plurality of parallel trenches extending perpendicularly into a surface of said substrate of a first conductivity type;

a first end of said first plurality of trenches being laterally spaced from a first end of said second plurality of trenches by an invertible channel region;

the interior surfaces of each of said trenches being of a second conductivity type;

a source contact and a drain contact connected to respective second ends of said first and second plurality of trenches respectively; and

a MOSgate structure connected to said invertible channel region.

2. The device of claim 1, wherein said trenches are spaced by mesa regions, and wherein the charge of said first conductivity type of the mesa regions is at least approximately matched by the charge of the diffusion of said second conductivity type which lines said trenches.

3. The device of claim 2, wherein said first conductivity type is P and said second conductivity type is N.

4. The device of claim 2, wherein said device is free of a termination.

5. The device of claim 1, wherein said first conductivity type is P and said second conductivity type is N.

6. The device of claim 5, wherein said device is free of a termination.

7. The device of claim 1, wherein said device is free of a termination.

8. A bidirectional conduction superjunction device comprising a substrate of the first conductivity;

and a plurality of thin layers formed atop said substrate and stacked atop one another and lying in planes parallel to one another;

said layers alternating in conductivity from a second conductivity type to said first conductivity type;

a drain diffusion of said second conductivity type disposed adjacent to and connected to one end of each of said layers;

a trench gate structure formed in said substrate and having one wall extending along the opposite ends of each of said layers;

a gate oxide lining the interior of said trench gate an a conductivity gate material filling the interior of said trench;

a source diffusion of said second conductivity type adjacent a second wall of said trench and said gate structure including a bottom portion extending between said one wall and said second wall of said trench; and

a source and drain contact connected to said source and drain diffusions respectively;

whereby the application of a potential to said conductive gate material enables conduction between said source and drain electrodes through a conduction path that includes a portion adjacent said bottom portion of said trench.

9. The device of claim 8, wherein the total charge in each of said layers is approximately the same.

10. The device of claim 9, wherein said first conductivity is P and said second conductivity type is N.

11. The device of claim 8, wherein said first conductivity is P and said second conductivity type is N.

12. The device of claim 8, wherein each of said layers has the same thickness.

13. The device of claim 12, wherein each of said layers is about 0.75 microns thick.

14. The device of claim 8, wherein each of said layers has a concentration of about 1.5×

10¹⁶ impurity carriers per cm³.

15. A bidirectional superjunction device comprising a plurality of laterally extending regions of alternately opposite conductivity type;

a drain region connected to one end of said laterally extending regions and a source region connected to the opposite end of said laterally extending regions;

a source electrode and a drain electrode connected to said source and drain regions respectively; and

a MOSgate structure coupled to said laterally extending regions and disposed between said source and drain regions and controlling conduction between said source and drain regions;

wherein said laterally extending regions are defined by parallel trenches in a substrate of a first conductivity type, and diffusions of the opposite conductivity type in the walls of said trenches; and

said MOSgate structure is disposed between said laterally extending trenches.

16. The device of claim 15, wherein adjacent ones of said laterally extending regions are charge balanced.

17. The device of claim 16, wherein said laterally extending regions are disposed as flat layers atop the surface of a silicon substrate.

18. The device of claim 17, wherein said MOSgate structure is a gate trench disposed between one end of said laterally extending regions and said source region;

said gate trench having a gate oxide liner and is filled with a conductive gate.