Low dielectric constant material for integrated circuit fabrication

• US 6,835,995 B2
• Filed: 12/27/2001
• Issued: 12/28/2004
• Est. Priority Date: 09/03/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Li, Weimin
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US10/033,656
• Publication Number:
  US 20020105084A1
• Time in Patent Office: 1,097 Days
• Field of Search: 257/499, 257/503, 257/506, 257/508, 257/632, 257/758
• US Class Current: 257/506
• CPC Class Codes: C23C 16/30 Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing

Abstract

A method is provided for forming a material with a low dielectric constant, suitable for electrical isolation in integrated circuits. The material and method of manufacture has particular use as an interlevel dielectric between metal lines in integrated circuits. In a disclosed embodiment, methylsilane is reacted with hydrogen peroxide to deposit a silicon hydroxide layer incorporating carbon. The layer is then treated by exposure to a plasma containing oxygen, and annealing the layer at a temperature of higher than about 450° C. or higher.

Claims

1. An interconnect structure comprising:

a first planar network of electrical conductors formed in a first deposition process;

a second planar network of electrical conductors formed in a second deposition process, and separated from the first planar network by a separation region; and

a single interlevel dielectric material disposed within the separation region and extending into a portion of the first planar network, without other intervening insulating materials between the first and second planar networks, such that the interlevel dielectric material has a planarized surface that interfaces the second planar network of electrical conductors, the interlevel dielectric material comprising a polysiloxane network consisting essentially of silicon, oxygen, carbon and hydrogen and incorporating carbon-silicon bonding and having a dielectric constant of less than about 3.3.

2. The interconnect structure of claim 1, wherein the interlevel dielectric material has a dielectric constant of less than about 3.2.

3. The interconnect structure of claim 1, wherein the interlevel dielectric material has a carbon content of between about 5% and 20% relative to a silicon content.

4. The interconnect structure of claim 1, wherein the first and second planar networks comprise metal runners.

5. An integrated circuit comprising:

a first planar network of electrical conductors formed in a first deposition process, and providing a first electrical path of the circuit;

a second planar network of electrical conductors formed in a second deposition process, and providing a second electrical path of the circuit, the second planar network separated from the first planar network by a gap; and

an interlevel dielectric material directly contacting the first and second planar networks, filling the gap between the first and second planar networks, having a planarized surface interfacing with the second planar network, and extending into a portion of the first planar network, the interlevel dielectric material comprising polysiloxane, consisting essentially of silicon, oxygen, carbon and hydrogen and incorporating carbon therein and having a dielectric constant of less than about 3.5.

6. The integrated circuit of claim 5, wherein the interlevel dielectric material has a dielectric constant of less than about 3.3.

7. The integrated circuit of claim 6, wherein the first and second planar networks comprise metal runners.

8. The integrated circuit of claim 6, wherein the first and second planar networks comprise transistor active areas within a semiconductor substrate.

9. The integrated circuit of claim 8, wherein the interlevel dielectric material comprises a sidewall spacer.