Antifuse structure and method of use

• US 6,836,000 B1
• Filed: 03/01/2000
• Issued: 12/28/2004
• Est. Priority Date: 03/01/2000
• Status: Expired due to Fees

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W., Batra, Shubneesh
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US09/515,760
• Time in Patent Office: 1,763 Days
• Field of Search: 257/530, 257/529, 257/50, 257/209, 438/131, 438/467, 438/600, 438/957, 438/132
• US Class Current: 257/530
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10S 257/928 with shorted PN or schottky junction other than emitter junction

Abstract

An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programming voltage is coupled to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse. The first programming voltage may be coupled to an ohmic contact in the well in the antifuse.

Claims

1. An antifuse comprising:

a well of a first conductivity type in a substrate of a second conductivity type;

a first conductive terminal of the second conductivity type; and

an insulator between the well and the first conductive terminal.

2. The antifuse of claim 1, further comprising an ohmic contact in the well as a second conductive terminal.

3. The antifuse of claim 2 wherein:

the substrate comprises a p-type silicon substrate;

the well comprises a n-type well in the substrate;

the ohmic contact comprises an n+-type diffusion region;

the insulator comprises a layer of oxide; and

the first conductive terminal comprises a layer of p-type polysilicon.

4. The antifuse of claim 2 wherein:

the substrate comprises a n-type silicon substrate;

the well comprises a p-type well in the substrate;

the ohmic contact comprises an p+-type diffusion region;

the insulator comprises a layer of oxide; and

the first conductive terminal comprises a layer of n-type polysilicon.

5. An integrated circuit comprising:

a first circuit;

a second circuit; and

an antifuse coupled between the first circuit and the second circuit, the antifuse comprising;

a well of a first conductivity type in a substrate of a second conductivity type;

a first conductivity terminal of the second conductivity type; and

an insulator between the well and the first conductivity terminal.

6. The integrated circuit of claim 5, further comprising an ohmic contact in the well as a second conductive terminal.

7. The integrated circuit of claim 6 wherein:

the substrate comprises a p-type silicon substrate;

the well comprises an n-type well in the substrate;

the ohmic contact comprises an n+-type diffusion region;

the insulator comprises a layer of oxide;

the first conductive terminal comprises a layer of p-type polysilicon;

the first circuit comprises a programming logic circuit; and

the second circuit comprises an external pin and a bias circuit.

8. The integrated circuit of claim 6 wherein:

the substrate comprises a n-type silicon substrate;

the well comprises an p-type well in the substrate;

the ohmic contact comprises an p+-type diffusion region;

the insulator comprises a layer of oxide;

the first conductive terminal comprises a layer of n-type polysilicon;

the first circuit comprises a programming logic circuit; and

the second circuit comprises an external pin and a bias circuit.

9. The integrated circuit of claim 5 wherein the integrated circuit comprises a memory device and further comprises an array of memory cells, an address decoder, a plurality of input/output paths, and an input/output control circuit.

10. An integrated circuit comprising:

a programming logic circuit;

an external pin; and

a plurality of antifuses, each antifuse comprising;

a well of a first conductivity type in a substrate of a second conductivity type, the well being coupled to the external pin;

a first conductive terminal of the second conductivity type coupled to the programming logic circuit; and

an insulator between the well and the first conductive terminal.

11. The integrated circuit of claim 10, further comprising an ohmic contact in the well coupled to the external pin.

12. The integrated circuit of claim 11 wherein:

the substrate comprises a p-type silicon substrate;

the well comprises an n-type well in the substrate;

the ohmic contact comprises an n+-type diffusion region;

the insulator comprises a layer of oxide; and

the first conductive terminal comprises a layer of p-type polysilicon.

13. The integrated circuit of claim 11 wherein:

the substrate comprises a n-type silicon substrate;

the well comprises an p-type well in the substrate;

the ohmic contact comprises an p+-type diffusion region;

the insulator comprises a layer of oxide; and

the first conductive terminal comprises a layer of n-type polysilicon.

14. The integrated circuit of claim 10 wherein the integrated circuit comprises a memory device and further comprises an array of memory cells, an address decoder, a plurality of input/output paths, and an input/output control circuit.

15. An antifuse bank comprising:

a programming logic circuit;

an external pin; and

a plurality of antifuses, each antifuse comprising;

a well of a first conductivity type in a substrate of a second conductivity type, the well being coupled to the external pin;

a first conductive terminal of the second conductivity type coupled to the programming logic circuit; and

an insulator between the well and the first conductive terminal.

16. The antifuse bank of claim 15, further comprising an ohmic contact in the well coupled to the external pin.

17. The antifuse bank of claim 16 wherein:

the substrate comprises a p-type silicon substrate;

the well comprises an n-type well in the substrate;

the ohmic contact comprises an n+-type diffusion region;

the insulator comprises a layer of oxide; and

the first conductive terminal comprises a layer of p-type polysilicon.

18. The antifuse bank of claim 16 wherein:

the substrate comprises a n-type silicon substrate;

the well comprises an p-type well in the substrate;

the ohmic contact comprises an p+-type diffusion region;

the insulator comprises a layer of oxide; and

the first conductive terminal comprises a layer of n-type polysilicon.

19. A method comprising:

coupling a first programming voltage to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse; and

coupling a second programming voltage to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse.

20. The method of claim 19 wherein coupling a first programming voltage comprises coupling a first programming voltage to an ohmic contact in the well of the first conductivity terminal and the substrate of the second conductivity type in the antifuse.

21. The method of claim 20 wherein:

coupling a first programming voltage comprises coupling a very high positive voltage to an n+-type diffusion region in an n-type well in a p-type substrate in an antifuse; and

coupling a second programming voltage comprises coupling a ground voltage reference to a layer of p-type polysilicon in the antifuse to create a current path through an insulating layer of oxide between the layer of p-type polysilicon and the n-type well to program the antifuse.

22. The method of claim 20 wherein:

coupling a first programming voltage comprises coupling a very negative positive voltage to a p+-type diffusion region in an p-type well in a n-type substrate in an antifuse; and

coupling a second programming voltage comprises coupling a supply voltage to a layer of n-type polysilicon in the antifuse to create a current path through an insulating layer of oxide between the layer of n-type polysilicon and the p-type well to program the antifuse.

23. A method of operating an integrated circuit comprising:

selecting an antifuse coupled between a first circuit and a second circuit in an integrated circuit;

coupling a first programming voltage to a well of a conductivity type in a substrate of a second conductivity type in the selected antifuse; and

coupling a second programming voltage to a conductive terminal of the second conductivity type in the selected antifuse to create a current path through an insulator between the conductive terminal and the well to program the selected antifuse.

24. The method of claim 23 wherein coupling a first programming voltage comprises coupling a first programming voltage to an ohmic contact in the well of the first conductivity type in the substrate of the second conductivity type in the selected antifuse.

25. The method of claim 24 wherein:

selecting an antifuse comprises selecting an antifuse from a plurality of antifuses coupled between a programming logic circuit and an external pin coupled to a bias circuit in the integrated circuit;

coupling a first programming voltage comprises a very high positive voltage to the external pin that is coupled to an n+-type diffusion region in an n-type well in a p-type substrate in the selected antifuse; and

coupling a second programming voltage comprises a ground voltage reference from the programming logic circuit to a layer of p-type polysilicon in the selected antifuse to create a current path through an insulating layer of oxide between the layer of p-type polysilicon and then n-type well to program the selected antifuse.

26. The method of claim 24 wherein:

selecting an antifuse comprises selecting an antifuse from a plurality of antifuses coupled between a programming logic circuit and an external pin coupled to a bias circuit in the integrated circuit;

coupling a first programming voltage comprises a very negative voltage to the external pin that is coupled to an p+-type diffusion region in an p-type well in a p-type substrate in the selected antifuse; and

coupling a second programming voltage comprises a supply voltage from the programming logic circuit to a layer of n-type polysilicon in the selected antifuse to create a current path through an insulating layer of oxide between the layer of n-type polysilicon and then p-type well to program the selected antifuse.

27. A method of operating an integrated circuit comprising:

selecting an antifuse coupled between a first circuit and a second circuit in an integrated circuit;

coupling a first programming voltage to a well of a conductivity type in a substrate of a second conductivity type in the selected antifuse; and

coupling a second programming voltage to a conductive terminal of the second conductivity type in the selected antifuse to create a current path through an insulator between the conductive terminal and the well to program the selected antifuse.

28. The method of claim 27 wherein coupling a first programming voltage comprises coupling a first programming voltage to the external pin that is coupled to an ohmic contact in the well of the first conductivity type in the substrate of the second conductivity type in the selected antifuse.

29. The method of claim 28 wherein:

selecting an antifuse comprises selecting an antifuse from a plurality of antifuses coupled between a programming logic circuit and an external pin coupled to a bias circuit in the integrated circuit;

coupling a first programming voltage comprises a very high positive voltage to the external pin that is coupled to an n+-type diffusion region in an n-type well in a p-type substrate in the selected antifuse; and

coupling a second programming voltage comprises a ground voltage reference from the programming logic circuit to a layer of p-type polysilicon in the selected antifuse to create a current path through an insulating layer of oxide between the layer of p-type polysilicon and then n-type well to program the selected antifuse.

30. The method of claim 28 wherein:

selecting an antifuse comprises selecting an antifuse from a plurality of antifuses coupled between a programming logic circuit and an external pin coupled to a bias circuit in the integrated circuit;

coupling a first programming voltage comprises a very negative voltage to the external pin that is coupled to an p+-type diffusion region in an p-type well in a n-type substrate in the selected antifuse; and

coupling a second programming voltage comprises a supply voltage from the programming logic circuit to a layer of n-type polysilicon in the selected antifuse to create a current path through an insulating layer of oxide between the layer of n-type polysilicon and then p-type well to program the selected antifuse.

31. A method comprising:

selecting circuits in a system to be coupled together;

programming an antifuse in the system to couple two or more of the selected circuits together, comprising;

coupling a first programming voltage to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse; and

coupling a second programming voltage to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse.

32. The method of claim 31 wherein coupling a first programming voltage comprises coupling a first programming voltage to an ohmic contact in the well of the first conductivity type in the substrate of the second conductivity type in the selected antifuse.

33. The method of claim 32 wherein:

coupling a first programming voltage comprises coupling a very high positive voltage to an n+-type diffusion region in an n-type well in a p-type substrate in an antifuse; and

coupling a second programming voltage comprises coupling a ground voltage reference to a layer of p-type polysilicon in the antifuse to create a current path through an insulating layer of oxide between the layer of p-type polysilicon and the n-type well to program the antifuse.

34. The method of claim 32 wherein:

coupling a first programming voltage comprises coupling a very negative positive voltage to a p+-type diffusion region in an p-type well in a n-type substrate in an antifuse; and

coupling a second programming voltage comprises coupling a supply voltage to a layer of n-type polysilicon in the antifuse to create a current path through an insulating layer of oxide between the layer of n-type polysilicon and the p-type well to program the antifuse.

35. A method of forming an antifuse comprising:

forming a well of a first conductivity type in a substrate of a second conductivity type;

forming an insulator over the well; and

forming a first conductive terminal of the second conductivity type over the insulator.

36. The method of claim 35, further comprising forming an ohmic contact in the well as a second conductive terminal.

37. The method of claim 35 wherein:

forming a well comprises forming an n-type well in a p-type silicon substrate and further comprises;

forming an n+-type drain diffusion in the well;

forming an n+-type source diffusion in the well;

forming an insulator comprises forming a layer of oxide over the well between the drain diffusion region and the source diffusion region; and

forming a first conductive terminal comprises forming a p-type polysilicon gate electrode over the layer of oxide.

38. The method of claim 35 wherein:

forming a well comprises forming an p-type well in a n-type silicon substrate and further comprises;

forming an p+-type drain diffusion in the well;

forming an p+-type source diffusion in the well;

forming an insulator comprises forming a layer of oxide over the well between the drain diffusion region and the source diffusion region; and

forming a first conductive terminal comprises forming a n-type polysilicon gate electrode over the layer of oxide.