Structure of integrated trace of chip package

• US 6,836,023 B2
• Filed: 04/14/2003
• Issued: 12/28/2004
• Est. Priority Date: 04/17/2002
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Joshi, Rajeev, Wu, Chung-Lin
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US10/413,796
• Publication Number:
  US 20030197278A1
• Time in Patent Office: 624 Days
• Field of Search: 257/781, 257/784, 257/736, 257/737, 257/738, 257/780, 257/779
• US Class Current: 257/780
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 23/492 Bases or plates or solder therefor
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor die package is disclosed. The die package includes a semiconductor die having a first side and a second side, a vertical transistor, and a bond pad at the first side. A passivation layer having a first aperture is on the first side, and the bond pad is exposed through the first aperture. An underbump metallurgy layer is on and in direct contact with the passivation layer. The underbump metallurgy layer is within the first aperture and contacts the bond pad. A dielectric layer comprising a second aperture is on and in direct contact with the underbump metallurgy layer. A solder structure is on the underbump metallurgy layer and is within the second aperture of the dielectric layer.

Claims

1. A semiconductor die package comprising:

(a) a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side;

(b) a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture;

(c) an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad;

(d) a single dielectric layer comprising a second aperture on and in direct contact with the underbump metallurgy layer; and

(e) a solder structure on the widerbump metallurgy layer, the solder structure being within the second aperture of the single dielectric layers,

wherein the vertical transistor comprises a power MOSFET comprising a gate region, a source region, and a drain region, wherein the gate region and the source region are at the first side of the semiconductor die, and the drain region is at the second side of the semiconductor die.

2. The semiconductor die package of claim 1 wherein the first aperture in the passivation layer and the second aperture in the single dielectric layer are not aligned.

4. The semiconductor die package of claim 1 wherein the gate region comprises a trenched gate.

5. The semiconductor die package of claim 1 wherein the underbump metallurgy layer comprises two or more sublayers of metal.

7. The semiconductor die package of claim 1 wherein the single dielectric layer comprises at least one selected from the group consisting of polyimide, benzcyclobutane, a nitride, and an oxide.

19. The semiconductor die package of claim 1 wherein the underbump metallurgy layer comprises a first sublayer, a second sublayer, and a third sublayer, wherein the first sub layer comprises Au or Ni, the second sublayer comprises Cu or Ni, and the third sublayer comprises Ti or TiW.

3. A semiconductor die package comprising:

(a) a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side;

(b) a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture;

(c) an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad;

(d) a single dielectric layer comprising a second aperture on and in direct contact with the underbump metallurgy layer; and

(e) a solder structure on the underbump metallurgy layer, the solder structure being within the second aperture of the single dielectric layer, wherein the first aperture in the passivation layer and the second aperture in the dielectric layer are aligned.

6. A semiconductor die package comprising:

(a) a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side;

(b) a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture;

(c) an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad;

(d) a single dielectric layer comprising a second aperture on and in direct contact with the underbump metallurgy layer; and

(e) a solder structure on the underbump metallurgy layer, the solder structure being within the second aperture of the single dielectric layer,

wherein the underbump metallurgy layer comprises a first sublayer, a second sublayer, and a third sublayer, wherein the first sublayer comprises Au or Ni, the second sublayer comprises Cu or Ni, and the third sublayer comprises Ti or TiW.

8. A method comprising:

(a) providing a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side;

(b) forming a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture;

(c) forming an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad;

(d) forming a single dielectric layer over the underbump metallurgy layer, wherein the single dielectric layer comprises a second aperture on and in direct contact with the underbump metallurgy layer; and

(e) forming a solder structure on the underbump metallurgy layer and within the second aperture of the dielectric layer,

wherein the vertical transistor comprises a power MOSFET comprising a gate region, a source region, and a drain region, wherein the gate region and the source region are at the first side of the semiconductor die, and the drain region is at the second side of the semiconductor die.

9. The method of claim 8 wherein the first aperture in the passivation layer and the second aperture in the dielectric layer are not aligned.

11. The method of claim 8 wherein the gate region comprises a trenched gate.

12. The method of claim 8 wherein the underbump metallurgy layer comprises two or more sublayer of metal.

14. The method of claim 8 wherein the dielectric layer comprises at least one selected from the group consisting of polyimide, benzcyclobutane, a nitride and an oxide.

20. The method of claim 8 wherein the underbump metallurgy layer comprises a first sublayer, a second sublayer, and a third sublayer, wherein the first sublayer comprises Au or Ni, the second sublayer comprises Cu or Ni, and the third sublayer comprises Ti or TiW.

10. A method comprising:

(a) providing a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side;

(b) forming a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture;

(c) forming an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad;

(d) forming a single dielectric layer over the underbump metallurgy layer, wherein the single dielectric layer comprises a second aperture on and in direct contact with the underbump metallurgy layer; and

(e) forming a solder structure on the underbump metallurgy layer and within the second aperture of the dielectric layer,

wherein the first aperture in the passivation layer and the second aperture in the dielectric layer are aligned.

13. A method comprising:

(a) providing a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side;

(b) forming a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture;

(c) forming an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad;

(d) forming a single dielectric layer over the underbump metallurgy layer, wherein the single dielectric layer comprises a second aperture on and in direct contact with the underbump metallurgy layer; and

(e) forming a solder structure on the underbump metallurgy layer and within the second aperture of the dielectric layer,

wherein the underbump metallurgy layer comprises a first sublayer, a second sublayer, and a third sublayer, wherein the first sublayer comprises Au or Ni, the second sublayer comprises Cu or Ni, and the third sublayer comprises Ti or TiW.

15. An electrical assembly comprising:

(a) a circuit substrate including a plurality of conductive regions; and

(b) a semiconductor die package comprising (i) a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side, (ii) a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture, (iii) an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad, (iv) a single dielectric layer comprising a second aperture on and in direct contact with the underbump metallurgy layer, and (v) a solder structure on the underbump metallurgy layer, the solder structure being within the second aperture of the single dielectric layer,

wherein the solder structure is coupled to a conductive region within the plurality of conductive regions.

16. The electrical assembly of claim 15 wherein the conductive region is a first conductive region, and wherein the electrical assembly further comprises a drain clip coupled to the second side of the semiconductor die and a second conductive region within the plurality of conductive regions.

17. The electrical assembly of claim 15 wherein the single dielectric layer comprises an inorganic material.

18. The electrical assembly of claim 15 wherein the first and second apertures are not aligned.