Single ended clock signal generator having a differential output

• US 6,836,169 B2
• Filed: 12/20/2002
• Issued: 12/28/2004
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Richmond, Greg, Akyildiz, Ahmet, Shkidt, Alex
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US10/327,217
• Publication Number:
  US 20040119509A1
• Time in Patent Office: 739 Days
• Field of Search: 327/291, 327/292, 327/295, 327/170, 327/172-176, 327/41, 327/43-45, 327/47, 327/49, 327/100-102, 327/199, 327/141-145
• US Class Current: 327/291
• CPC Class Codes: H03K 5/151 with two complementary outputs

Abstract

Embodiments of the present invention provide for generating a sampled differential pattern signal with reduced jitter. In one embodiment of the present invention, a seed frequency generator provides a differential seed frequency signal. The differential seed frequency signal is converted to a single ended seed frequency signal by a differential-to-single ended converter. The pattern generation logic utilizes the single ended seed frequency signal to generate single ended pattern signals. Single ended-to-differential samplers then generate a sampled differential pattern signal by sampling the single ended pattern signal according to the differential seed frequency signal.

Claims

1. A pattern generator comprising:

a converter for converting a differential seed frequency signal to a single ended seed frequency signal;

a pattern generation logic coupled to said converter and for generating a single ended pattern signal from said single ended seed frequency signal; and

a single-to-differential sampler coupled to said pattern generation logic and for generating a sampled differential pattern signal based on said single ended pattern signal, wherein said single-to-differential sampler is clocked by a differential clock signal.

2. The pattern generator according to claim 1, further comprising a seed frequency generator coupled to said converter and for providing said differential seed frequency signal.

3. The pattern generator according to claim 2, wherein said pattern generation logic is a low power circuit and wherein said differential seed frequency signal is generated by said seed frequency generator.

4. The pattern generator according to claim 1, wherein noise present on said single ended pattern signal is reduced in said sampled differential pattern signal.

5. The pattern generator according to claim 1, wherein said sampled differential pattern signal generated by said single-to-differential sampler is substantially jitter free.

6. The pattern generator according to claim 1, wherein said pattern generation logic reduces fabrication area occupied by said pattern generator.

7. A pattern generator comprising:

a single ended pattern generation logic generating a single ended pattern signal from a single ended seed frequency signal;

a differential flip-flop coupled to said single ended pattern generation logic, wherein a sampled differential pattern signal is generated by said differential flip-flop by sampling said single ended pattern signal according to a differential seed frequency signal; and

a re-synchronization flip-flop coupled between said single ended pattern generation logic and said differential flip-flop, wherein said single ended pattern signal is re-synchronized by said re-synchronization flip-flop to said single ended seed frequency signal.

8. The pattern generator according to claim 7, further comprising a complimentary flip-flop coupled between said single ended pattern generation logic and said differential flip-flop, wherein said single ended pattern signal is converted by said complimentary flip-flop to a complimentary single ended clock signal.

9. The pattern generator according to claim 7, further comprising a phase lock loop voltage controlled oscillator coupled to said single ended pattern generation logic.

10. The pattern generator according to claim 9, further comprising a converter coupled between said phase lock loop voltage controlled oscillator and said single ended pattern generation logic, wherein a differential seed frequency signal is converted by said converter to said single ended seed frequency signal and wherein said phase lock loop voltage controlled oscillator also generates said differential seed frequency signal.

11. The pattern generator according to claim 7, wherein jitter on said sampled differential pattern signal is reduced.

12. The pattern generator according to claim 7, further comprising:

a latch couple to said sampled differential pattern signal and for generating a latched sampled differential pattern signal, wherein said sampled differential pattern signal is latched by said differential clock signal; and

an or-gate coupled to said sampled differential pattern and said latched sampled differential pattern signal and generating a fifty percent duty cycle sampled differential pattern signal.

13. The pattern generator according to claim 7, further comprising a second converter, wherein said sampled differential pattern signal is converted by said second converter to a sampled single ended pattern signal.

14. A method of generating a reduced jitter signal comprising:

converting a differential seed frequency signal to a single ended seed frequency signal;

generating a single ended pattern signal from said single ended seed frequency signal; and

converting said single ended pattern signal to a sampled differential pattern signal by sampling said single ended pattern signal at a transition crossing of said differential seed frequency signal.

15. The method of claim 14, further comprising generating said differential seed frequency signal.

16. The method of claim 14, wherein jitter present on said single ended pattern signal is reduced in said sampled differential pattern signal by sampling based upon said single ended seed frequency.

17. The method of claim 14, further comprising re-synchronizing said single ended pattern signal to said single ended seed frequency signal.

18. The method of claim 14, further comprising converting said single ended pattern signal to a complimentary single ended clock signal.

19. The method of claim 14, further comprising:

latching said sampled differential pattern signal as a function of said differential clock signal; and

generating a fifty percent duty cycle sampled differential pattern signal as a function of said sampled differential pattern signal and said latched sampled differential pattern signal.

20. The method of claim 14, further comprising converting said sampled differential pattern signal to a sampled single ended pattern signal.

21. A pattern generator comprising:

a converter having a first and second input for receiving a differential seed frequency signal;

a pattern generation logic having a first input coupled to an output of said converter;

a differential flip-flop having a first input coupled to an output of said pattern generation logic, having a differential clock input for receiving said differential seed frequency signal, and wherein a sampled differential pattern signal is output at a first and second output of said differential flip-flop.

22. The pattern generator according to claim 21, further comprising a compliment re-synchronize flip-flop having a first input coupled to said output of said pattern generation logic, having a clock input coupled to said output of said converter, having a first output coupled to said first input of said differential flip-flop and having a second output coupled to said second input of said differential flip-flop.

23. The pattern generator according to claim 21, further comprising:

a latch having a first input coupled to said first output of said differential flip-flop, having a second input coupled to said second output of said differential flip-flop, having a third and fourth input for receiving said differential seed frequency signal; and

an or-gate having a first input coupled to said first output of said differential flip-flop, having a second input coupled to a first output of said latch, having a third input coupled to said second output of said differential flip-flop, having a fourth input coupled to a second output of said latch, and wherein a sampled differential pattern signal having a stretched pulse is output at a first and second output of said or-gate.

24. A pattern generator comprising:

a single ended pattern generation logic generating a single ended pattern signal from a single ended seed frequency signal;

a differential flip-flop coupled to said single ended pattern generation logic, wherein a sampled differential pattern signal is generated by said differential flip-flop by sampling said single ended pattern signal according to a differential seed frequency signal;

a latch couple to said sampled differential pattern signal and for generating a latched sampled differential pattern signal, wherein said sampled differential pattern signal is latched by said differential clock signal; and

an or-gate coupled to said sampled differential pattern and said latched sampled differential pattern signal and generating a fifty percent duty cycle sampled differential pattern signal.

25. The pattern generator according to claim 24, further comprising a complimentary flip-flop coupled between said single ended pattern generation logic and said differential flip-flop, wherein said single ended pattern signal is converted by said complimentary flip-flop to a complimentary single ended clock signal.

26. The pattern generator according to claim 24, further comprising a re-synchronization flip-flop coupled between said single ended pattern generation logic and said differential flip-flop, wherein said single ended pattern signal is re-synchronized by said re-synchronization flip-flop to said single ended seed frequency signal.

27. The pattern generator according to claim 24, further comprising:

a phase lock loop voltage controlled oscillator for generating said differential seed frequency signal; and

a converter coupled between said phase lock loop voltage controlled oscillator and said single ended pattern generation logic for converting said differential seed frequency signal to said single ended seed frequency signal.

28. The pattern generator according to claim 24, further comprising a converter, wherein said sampled differential pattern signal is converted by said converter to a sampled single ended pattern signal.